1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 110 unchanged lines hidden (view full) ---

119 if (i->second->used) {
120 i->second->used = false;
121 usedEntries--;
122 }
123 DPRINTF(TLB, "TLB: Found conflicting entry, deleting it\n");
124 lookupTable.erase(i);
125 }
126
127 lookupTable.insert(new_entry->range, new_entry);;
128
129 // If all entries have there used bit set, clear it on them all, but the
130 // one we just inserted
131 if (usedEntries == size) {
132 clearUsedBits();
133 new_entry->used = true;
134 usedEntries++;
135 }

--- 7 unchanged lines hidden (view full) ---

143 MapIter i;
144 TlbRange tr;
145 TlbEntry *t;
146
147 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
148 va, partition_id, context_id, real);
149 // Assemble full address structure
150 tr.va = va;
151 tr.size = va + MachineBytes;
152 tr.contextId = context_id;
153 tr.partitionId = partition_id;
154 tr.real = real;
155
156 // Try to find the entry
157 i = lookupTable.find(tr);
158 if (i == lookupTable.end()) {
159 DPRINTF(TLB, "TLB: No valid entry found\n");

--- 15 unchanged lines hidden (view full) ---

175 }
176
177 return t;
178}
179
180void
181TLB::dumpAll()
182{
183 for (int x = 0; x < size; x++) {
184 if (tlb[x].valid) {
185 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
186 x, tlb[x].range.partitionId, tlb[x].range.contextId,
187 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
188 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
189 }
190 }
191}
192
193void
194TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
195{
196 TlbRange tr;
197 MapIter i;
198
199 cacheValid = false;
200
201 // Assemble full address structure
202 tr.va = va;
203 tr.size = va + MachineBytes;
204 tr.contextId = context_id;
205 tr.partitionId = partition_id;
206 tr.real = real;
207
208 // Demap any entry that conflicts
209 i = lookupTable.find(tr);
210 if (i != lookupTable.end()) {
211 i->second->valid = false;
212 if (i->second->used) {
213 i->second->used = false;
214 usedEntries--;
215 }
216 lookupTable.erase(i);
217 }
218}
219
220void
221TLB::demapContext(int partition_id, int context_id)
222{
223 int x;
224 cacheValid = false;
225 for (x = 0; x < size; x++) {
226 if (tlb[x].range.contextId == context_id &&
227 tlb[x].range.partitionId == partition_id) {
228 tlb[x].valid = false;
229 if (tlb[x].used) {
230 tlb[x].used = false;
231 usedEntries--;
232 }
233 lookupTable.erase(tlb[x].range);
234 }
235 }
236}
237
238void
239TLB::demapAll(int partition_id)
240{
241 int x;
242 cacheValid = false;
243 for (x = 0; x < size; x++) {
244 if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
245 tlb[x].valid = false;
246 if (tlb[x].used) {
247 tlb[x].used = false;
248 usedEntries--;
249 }

--- 629 unchanged lines hidden (view full) ---

879 ASI asi = (ASI)pkt->req->getAsi();
880
881 Addr ta_insert;
882 Addr va_insert;
883 Addr ct_insert;
884 int part_insert;
885 int entry_insert = -1;
886 bool real_insert;
887 PageTableEntry pte;
888
889 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
890 (uint32_t)asi, va, data);
891
892 switch (asi) {
893 case ASI_LSU_CONTROL_REG:
894 assert(va == 0);

--- 103 unchanged lines hidden (view full) ---

998 va_insert = mbits(ta_insert, 63,13);
999 ct_insert = mbits(ta_insert, 12,0);
1000 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1001 real_insert = bits(va, 9,9);
1002 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1003 PageTableEntry::sun4u);
1004 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1005 break;
1006 case ASI_DMMU:
1007 switch (va) {
1008 case 0x30:
1009 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1010 break;
1011 case 0x80:
1012 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1013 break;
1014 default:
1015 goto doMmuWriteError;
1016 }
1017 break;
1018 default:
1019doMmuWriteError:
1020 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1021 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1022 }
1023 pkt->result = Packet::Success;
1024 return tc->getCpuPtr()->cycles(1);
1025}

--- 56 unchanged lines hidden ---