1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 57 unchanged lines hidden (view full) ---

66 usedEntries--;
67 }
68 }
69}
70
71
72void
73TLB::insert(Addr va, int partition_id, int context_id, bool real,
74 const PageTableEntry& PTE)
75{
76
77
78 MapIter i;
79 TlbEntry *new_entry;
80
81 DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x, pid=%d cid=%d r=%d\n",
82 va, partition_id, context_id, (int)real);
83
84 int x = -1;
85 for (x = 0; x < size; x++) {
86 if (!tlb[x].valid || !tlb[x].used) {
87 new_entry = &tlb[x];
88 break;
89 }
90 }
91
92 // Update the last ently if their all locked
93 if (x == -1)
94 x = size - 1;
95
96 assert(PTE.valid());
97 new_entry->range.va = va;
98 new_entry->range.size = PTE.size();
99 new_entry->range.partitionId = partition_id;
100 new_entry->range.contextId = context_id;
101 new_entry->range.real = real;
102 new_entry->pte = PTE;

--- 44 unchanged lines hidden (view full) ---

147 tr.real = real;
148
149 // Try to find the entry
150 i = lookupTable.find(tr);
151 if (i == lookupTable.end()) {
152 DPRINTF(TLB, "TLB: No valid entry found\n");
153 return NULL;
154 }
155 DPRINTF(TLB, "TLB: Valid entry found\n");
156
157 // Mark the entries used bit and clear other used bits in needed
158 t = i->second;
159 if (!t->used) {
160 t->used = true;
161 usedEntries++;
162 if (usedEntries == size) {
163 clearUsedBits();
164 t->used = true;
165 usedEntries++;
166 }
167 }
168
169 return t;
170}
171
172
173void
174TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
175{
176 TlbRange tr;
177 MapIter i;
178
179 // Assemble full address structure

--- 100 unchanged lines hidden (view full) ---

280
281 if (write)
282 sfsr |= 1 << 2;
283 sfsr |= ct << 4;
284 if (se)
285 sfsr |= 1 << 6;
286 sfsr |= ft << 7;
287 sfsr |= asi << 16;
288 tc->setMiscReg(reg, sfsr);
289}
290
291
292void
293ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
294 bool se, FaultTypes ft, int asi)
295{
296 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n",
297 (int)write, ct, ft, asi);
298 TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
299}
300
301void
302DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
303 bool se, FaultTypes ft, int asi)
304{
305 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
306 a, (int)write, ct, ft, asi);
307 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
308 tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a);
309}
310
311
312Fault
313ITB::translate(RequestPtr &req, ThreadContext *tc)
314{
315 uint64_t hpstate = tc->readMiscReg(MISCREG_HPSTATE);
316 uint64_t pstate = tc->readMiscReg(MISCREG_PSTATE);
317 bool lsuIm = tc->readMiscReg(MISCREG_MMU_LSU_CTRL) >> 2 & 0x1;
318 uint64_t tl = tc->readMiscReg(MISCREG_TL);
319 uint64_t part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);

--- 24 unchanged lines hidden (view full) ---

344 }
345
346 if ( hpstate >> 2 & 0x1 || hpstate >> 5 & 0x1 ) {
347 req->setPaddr(req->getVaddr() & PAddrImplMask);
348 return NoFault;
349 }
350
351 // If the asi is unaligned trap
352 if (vaddr & 0x7) {
353 writeSfsr(tc, false, ct, false, OtherFault, asi);
354 return new MemAddressNotAligned;
355 }
356
357 if (addr_mask)
358 vaddr = vaddr & VAddrAMask;
359
360 if (!validVirtualAddress(vaddr, addr_mask)) {

--- 19 unchanged lines hidden (view full) ---

380 }
381
382 // were not priviledged accesing priv page
383 if (!priv && e->pte.priv()) {
384 writeSfsr(tc, false, ct, false, PrivViolation, asi);
385 return new InstructionAccessException;
386 }
387
388 req->setPaddr(e->pte.paddr() & ~e->pte.size() |
389 req->getVaddr() & e->pte.size());
390 return NoFault;
391}
392
393
394
395Fault
396DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
397{

--- 53 unchanged lines hidden (view full) ---

451 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
452 return new PrivilegedAction;
453 }
454 if (priv && AsiIsHPriv(asi)) {
455 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
456 return new DataAccessException;
457 }
458
459 }
460
461 // If the asi is unaligned trap
462 if (vaddr & size-1) {
463 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
464 return new MemAddressNotAligned;
465 }
466
467 if (addr_mask)
468 vaddr = vaddr & VAddrAMask;
469
470 if (!validVirtualAddress(vaddr, addr_mask)) {
471 writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
472 return new DataAccessException;
473 }
474
475 if (!implicit) {
476 if (AsiIsLittle(asi))
477 panic("Little Endian ASIs not supported\n");
478 if (AsiIsBlock(asi))
479 panic("Block ASIs not supported\n");
480 if (AsiIsNoFault(asi))
481 panic("No Fault ASIs not supported\n");
482 if (AsiIsTwin(asi))

--- 11 unchanged lines hidden (view full) ---

494 goto handleQueueRegAccess;
495 if (AsiIsSparcError(asi))
496 goto handleSparcErrorRegAccess;
497
498 if (!AsiIsReal(asi) && !AsiIsNucleus(asi))
499 panic("Accessing ASI %#X. Should we?\n", asi);
500 }
501
502 if ((!lsuDm && !hpriv) || AsiIsReal(asi)) {
503 real = true;
504 context = 0;
505 };
506
507 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
508 req->setPaddr(req->getVaddr() & PAddrImplMask);
509 return NoFault;

--- 27 unchanged lines hidden (view full) ---

537 req->setFlags(req->getFlags() | UNCACHEABLE);
538
539
540 if (!priv && e->pte.priv()) {
541 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
542 return new DataAccessException;
543 }
544
545 req->setPaddr(e->pte.paddr() & ~e->pte.size() |
546 req->getVaddr() & e->pte.size());
547 return NoFault;
548 /** Normal flow ends here. */
549
550handleScratchRegAccess:
551 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
552 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
553 return new DataAccessException;
554 }

--- 104 unchanged lines hidden (view full) ---

659 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
660 assert(va == 0);
661 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
662 break;
663 case ASI_IMMU_CTXT_NONZERO_CONFIG:
664 assert(va == 0);
665 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
666 break;
667 case ASI_HYP_SCRATCHPAD:
668 case ASI_SCRATCHPAD:
669 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
670 break;
671 case ASI_DMMU:
672 switch (va) {
673 case 0x80:
674 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
675 break;
676 default:
677 goto doMmuReadError;
678 }
679 break;
680 default:

--- 7 unchanged lines hidden (view full) ---

688
689Tick
690DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
691{
692 uint64_t data = gtoh(pkt->get<uint64_t>());
693 Addr va = pkt->getAddr();
694 ASI asi = (ASI)pkt->req->getAsi();
695
696 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
697 (uint32_t)asi, va, data);
698
699 switch (asi) {
700 case ASI_LSU_CONTROL_REG:
701 assert(va == 0);
702 tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
703 break;

--- 65 unchanged lines hidden (view full) ---

769 case ASI_SPARC_ERROR_EN_REG:
770 case ASI_SPARC_ERROR_STATUS_REG:
771 warn("Ignoring write to SPARC ERROR regsiter\n");
772 break;
773 case ASI_HYP_SCRATCHPAD:
774 case ASI_SCRATCHPAD:
775 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
776 break;
777 case ASI_DMMU:
778 switch (va) {
779 case 0x80:
780 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
781 break;
782 default:
783 goto doMmuWriteError;
784 }
785 break;
786 default:

--- 63 unchanged lines hidden ---