1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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323 int context;
324 ContextType ct;
325 int asi;
326 bool real = false;
327 TlbEntry *e;
328
329 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
330 vaddr, req->getSize());
331
332 assert(req->getAsi() == ASI_IMPLICIT);
333
334 if (tl > 0) {
335 asi = ASI_N;
336 ct = Nucleus;
337 context = 0;
338 } else {

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355 if (addr_mask)
356 vaddr = vaddr & VAddrAMask;
357
358 if (!validVirtualAddress(vaddr, addr_mask)) {
359 writeSfsr(tc, false, ct, false, VaOutOfRange, asi);
360 return new InstructionAccessException;
361 }
362
363 if (lsuIm) {
364 e = lookup(req->getVaddr(), part_id, true);
365 real = true;
366 context = 0;
367 } else {
368 e = lookup(vaddr, part_id, false, context);
369 }
370
371 if (e == NULL || !e->valid) {

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411 int context;
412 ASI asi;
413
414 TlbEntry *e;
415
416 asi = (ASI)req->getAsi();
417 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
418 vaddr, size, asi);
419
420 if (asi == ASI_IMPLICIT)
421 implicit = true;
422
423 if (implicit) {
424 if (tl > 0) {
425 asi = ASI_N;
426 ct = Nucleus;
427 context = 0;

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484 panic("Interrupt ASIs not supported\n");
485
486 if (AsiIsMmu(asi))
487 goto handleMmuRegAccess;
488 if (AsiIsScratchPad(asi))
489 goto handleScratchRegAccess;
490 if (AsiIsQueue(asi))
491 goto handleQueueRegAccess;
492
493 if (!AsiIsReal(asi) && !AsiIsNucleus(asi))
494 panic("Accessing ASI %#X. Should we?\n", asi);
495 }
496
497 if ((!lsuDm && !hpriv) || AsiIsReal(asi)) {
498 real = true;
499 context = 0;

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555 return new PrivilegedAction;
556 }
557 if (priv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
558 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
559 return new DataAccessException;
560 }
561 goto regAccessOk;
562
563regAccessOk:
564handleMmuRegAccess:
565 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
566 req->setMmapedIpr(true);
567 req->setPaddr(req->getVaddr());
568 return NoFault;
569};
570

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670
671Tick
672DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
673{
674 uint64_t data = gtoh(pkt->get<uint64_t>());
675 Addr va = pkt->getAddr();
676 ASI asi = (ASI)pkt->req->getAsi();
677
678 DPRINTF(IPR, "Memory Mapped IPR Write: asi=#%X a=%#x d=%#X\n",
679 (uint32_t)asi, va, data);
680
681 switch (asi) {
682 case ASI_LSU_CONTROL_REG:
683 assert(va == 0);
684 tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
685 break;
686 case ASI_MMU:

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691 case 0x10:
692 tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
693 break;
694 default:
695 goto doMmuWriteError;
696 }
697 break;
698 case ASI_QUEUE:
699 assert(mbits(va,13,6) == va);
700 tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
701 (va >> 4) - 0x3c, data);
702 break;
703 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
704 assert(va == 0);
705 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
706 break;
707 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:

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743 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
744 assert(va == 0);
745 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
746 break;
747 case ASI_IMMU_CTXT_NONZERO_CONFIG:
748 assert(va == 0);
749 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
750 break;
751 case ASI_HYP_SCRATCHPAD:
752 case ASI_SCRATCHPAD:
753 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
754 break;
755 case ASI_DMMU:
756 switch (va) {
757 case 0x80:
758 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);

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