1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/asi.hh"
32#include "arch/sparc/tlb.hh"
33#include "sim/builder.hh"
34#include "arch/sparc/miscregfile.hh"
35#include "cpu/thread_context.hh"
36
37/* @todo remove some of the magic constants. -- ali
38 * */
39namespace SparcISA
40{
41
42TLB::TLB(const std::string &name, int s)
43 : SimObject(name), size(s)

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67void
68TLB::insert(Addr va, int partition_id, int context_id, bool real,
69 const PageTableEntry& PTE)
70{
71
72
73 MapIter i;
74 TlbEntry *new_entry;
75 int x = -1;
76 for (x = 0; x < size; x++) {
77 if (!tlb[x].valid || !tlb[x].used) {
78 new_entry = &tlb[x];
79 break;
80 }
81 }
82

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99 // Demap any entry that conflicts
100 i = lookupTable.find(new_entry->range);
101 if (i != lookupTable.end()) {
102 i->second->valid = false;
103 if (i->second->used) {
104 i->second->used = false;
105 usedEntries--;
106 }
107 lookupTable.erase(i);
108 }
109
110 lookupTable.insert(new_entry->range, new_entry);;
111
112 // If all entries have there used bit set, clear it on them all, but the
113 // one we just inserted
114 if (usedEntries == size) {

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122
123TlbEntry*
124TLB::lookup(Addr va, int partition_id, bool real, int context_id)
125{
126 MapIter i;
127 TlbRange tr;
128 TlbEntry *t;
129
130 // Assemble full address structure
131 tr.va = va;
132 tr.size = va + MachineBytes;
133 tr.contextId = context_id;
134 tr.partitionId = partition_id;
135 tr.real = real;
136
137 // Try to find the entry
138 i = lookupTable.find(tr);
139 if (i == lookupTable.end()) {
140 return NULL;
141 }
142
143 // Mark the entries used bit and clear other used bits in needed
144 t = i->second;
145 if (!t->used) {
146 t->used = true;
147 usedEntries++;
148 if (usedEntries == size) {
149 clearUsedBits();

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274 tc->setMiscReg(reg, sfsr);
275}
276
277
278void
279ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
280 bool se, FaultTypes ft, int asi)
281{
282 TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
283}
284
285void
286DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
287 bool se, FaultTypes ft, int asi)
288{
289 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
290 tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a);
291}
292
293
294Fault
295ITB::translate(RequestPtr &req, ThreadContext *tc)
296{

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303 bool priv = pstate >> 2 & 0x1;
304 Addr vaddr = req->getVaddr();
305 int context;
306 ContextType ct;
307 int asi;
308 bool real = false;
309 TlbEntry *e;
310
311 assert(req->getAsi() == ASI_IMPLICIT);
312
313 if (tl > 0) {
314 asi = ASI_N;
315 ct = Nucleus;
316 context = 0;
317 } else {
318 asi = ASI_P;

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380 uint64_t part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
381 bool hpriv = hpstate >> 2 & 0x1;
382 bool red = hpstate >> 5 >> 0x1;
383 bool addr_mask = pstate >> 3 & 0x1;
384 bool priv = pstate >> 2 & 0x1;
385 bool implicit = false;
386 bool real = false;
387 Addr vaddr = req->getVaddr();
388 ContextType ct;
389 int context;
390 ASI asi;
391
392 TlbEntry *e;
393
394
395 asi = (ASI)req->getAsi();
396 if (asi == ASI_IMPLICIT)
397 implicit = true;
398
399 if (implicit) {
400 if (tl > 0) {
401 asi = ASI_N;
402 ct = Nucleus;
403 context = 0;

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427 if (priv && AsiIsHPriv(asi)) {
428 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
429 return new DataAccessException;
430 }
431
432 }
433
434 // If the asi is unaligned trap
435 if (AsiIsBlock(asi) && vaddr & 0x3f || vaddr & 0x7) {
436 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
437 return new MemAddressNotAligned;
438 }
439
440 if (addr_mask)
441 vaddr = vaddr & VAddrAMask;
442
443 if (!validVirtualAddress(vaddr, addr_mask)) {

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473 return NoFault;
474 }
475
476 e = lookup(req->getVaddr(), part_id, real, context);
477
478 if (e == NULL || !e->valid) {
479 tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS,
480 vaddr & ~BytesInPageMask | context);
481 if (real)
482 return new DataRealTranslationMiss;
483 else
484 return new FastDataAccessMMUMiss;
485
486 }
487
488

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511 /** Normal flow ends here. */
512
513handleScratchRegAccess:
514 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
515 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
516 return new DataAccessException;
517 }
518handleMmuRegAccess:
519 req->setMmapedIpr(true);
520 req->setPaddr(req->getVaddr());
521 return NoFault;
522};
523
524Tick
525DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
526{

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