registers.hh (7649:a6a6177a5ffa) | registers.hh (7741:340b6f01d69b) |
---|---|
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 25 unchanged lines hidden (view full) --- 34 35#include "arch/sparc/max_inst_regs.hh" 36#include "arch/sparc/miscregs.hh" 37#include "arch/sparc/sparc_traits.hh" 38#include "base/types.hh" 39 40namespace SparcISA 41{ | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 25 unchanged lines hidden (view full) --- 34 35#include "arch/sparc/max_inst_regs.hh" 36#include "arch/sparc/miscregs.hh" 37#include "arch/sparc/sparc_traits.hh" 38#include "base/types.hh" 39 40namespace SparcISA 41{ |
42 using SparcISAInst::MaxInstSrcRegs; 43 using SparcISAInst::MaxInstDestRegs; | |
44 | 42 |
45 typedef uint64_t IntReg; 46 typedef uint64_t MiscReg; 47 typedef float FloatReg; 48 typedef uint32_t FloatRegBits; 49 typedef union 50 { 51 IntReg intReg; 52 FloatReg fpreg; 53 MiscReg ctrlreg; 54 } AnyReg; | 43using SparcISAInst::MaxInstSrcRegs; 44using SparcISAInst::MaxInstDestRegs; |
55 | 45 |
56 typedef uint16_t RegIndex; | 46typedef uint64_t IntReg; 47typedef uint64_t MiscReg; 48typedef float FloatReg; 49typedef uint32_t FloatRegBits; 50typedef union 51{ 52 IntReg intReg; 53 FloatReg fpreg; 54 MiscReg ctrlreg; 55} AnyReg; |
57 | 56 |
58 // These enumerate all the registers for dependence tracking. 59 enum DependenceTags { 60 FP_Base_DepTag = 32*3+9, 61 Ctrl_Base_DepTag = FP_Base_DepTag + 64, 62 Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs 63 }; | 57typedef uint16_t RegIndex; |
64 | 58 |
65 // semantically meaningful register indices 66 const int ZeroReg = 0; // architecturally meaningful 67 // the rest of these depend on the ABI 68 const int ReturnAddressReg = 31; // post call, precall is 15 69 const int ReturnValueReg = 8; // Post return, 24 is pre-return. 70 const int StackPointerReg = 14; 71 const int FramePointerReg = 30; | 59// These enumerate all the registers for dependence tracking. 60enum DependenceTags { 61 FP_Base_DepTag = 32*3+9, 62 Ctrl_Base_DepTag = FP_Base_DepTag + 64, 63 Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs 64}; |
72 | 65 |
73 // Some OS syscall use a second register (o1) to return a second value 74 const int SyscallPseudoReturnReg = 9; | 66// semantically meaningful register indices 67const int ZeroReg = 0; // architecturally meaningful 68// the rest of these depend on the ABI 69const int ReturnAddressReg = 31; // post call, precall is 15 70const int ReturnValueReg = 8; // Post return, 24 is pre-return. 71const int StackPointerReg = 14; 72const int FramePointerReg = 30; |
75 | 73 |
76 const int NumIntArchRegs = 32; 77 const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; | 74// Some OS syscall use a second register (o1) to return a second value 75const int SyscallPseudoReturnReg = 9; |
78 | 76 |
77const int NumIntArchRegs = 32; 78const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; 79 |
|
79} // namespace SparcISA 80 81#endif | 80} // namespace SparcISA 81 82#endif |