registers.hh (6329:5d8b91875859) | registers.hh (7649:a6a6177a5ffa) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 44 unchanged lines hidden (view full) --- 53 MiscReg ctrlreg; 54 } AnyReg; 55 56 typedef uint16_t RegIndex; 57 58 // These enumerate all the registers for dependence tracking. 59 enum DependenceTags { 60 FP_Base_DepTag = 32*3+9, | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 44 unchanged lines hidden (view full) --- 53 MiscReg ctrlreg; 54 } AnyReg; 55 56 typedef uint16_t RegIndex; 57 58 // These enumerate all the registers for dependence tracking. 59 enum DependenceTags { 60 FP_Base_DepTag = 32*3+9, |
61 Ctrl_Base_DepTag = FP_Base_DepTag + 64 | 61 Ctrl_Base_DepTag = FP_Base_DepTag + 64, 62 Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs |
62 }; 63 64 // semantically meaningful register indices 65 const int ZeroReg = 0; // architecturally meaningful 66 // the rest of these depend on the ABI 67 const int ReturnAddressReg = 31; // post call, precall is 15 68 const int ReturnValueReg = 8; // Post return, 24 is pre-return. 69 const int StackPointerReg = 14; 70 const int FramePointerReg = 30; 71 72 // Some OS syscall use a second register (o1) to return a second value 73 const int SyscallPseudoReturnReg = 9; 74 75 const int NumIntArchRegs = 32; 76 const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; 77 78} // namespace SparcISA 79 80#endif | 63 }; 64 65 // semantically meaningful register indices 66 const int ZeroReg = 0; // architecturally meaningful 67 // the rest of these depend on the ABI 68 const int ReturnAddressReg = 31; // post call, precall is 15 69 const int ReturnValueReg = 8; // Post return, 24 is pre-return. 70 const int StackPointerReg = 14; 71 const int FramePointerReg = 30; 72 73 // Some OS syscall use a second register (o1) to return a second value 74 const int SyscallPseudoReturnReg = 9; 75 76 const int NumIntArchRegs = 32; 77 const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; 78 79} // namespace SparcISA 80 81#endif |