registers.hh (13386:3447b3202bb1) registers.hh (13556:9f57bb56153a)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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40
41namespace SparcISA
42{
43
44using SparcISAInst::MaxInstSrcRegs;
45using SparcISAInst::MaxInstDestRegs;
46using SparcISAInst::MaxMiscDestRegs;
47
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 31 unchanged lines hidden (view full) ---

40
41namespace SparcISA
42{
43
44using SparcISAInst::MaxInstSrcRegs;
45using SparcISAInst::MaxInstDestRegs;
46using SparcISAInst::MaxMiscDestRegs;
47
48typedef uint64_t IntReg;
49typedef uint64_t MiscReg;
50typedef double FloatReg;
51typedef uint64_t FloatRegBits;
48typedef RegVal IntReg;
49typedef RegVal MiscReg;
50typedef FloatRegVal FloatReg;
51typedef RegVal FloatRegBits;
52
53// dummy typedef since we don't have CC regs
54typedef uint8_t CCReg;
55
56// dummy typedefs since we don't have vector regs
57constexpr unsigned NumVecElemPerVecReg = 2;
58using VecElem = uint32_t;
59using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;

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53// dummy typedef since we don't have CC regs
54typedef uint8_t CCReg;
55
56// dummy typedefs since we don't have vector regs
57constexpr unsigned NumVecElemPerVecReg = 2;
58using VecElem = uint32_t;
59using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;

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