1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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52{
53 IntReg intReg;
54 FloatReg fpreg;
55 MiscReg ctrlreg;
56} AnyReg;
57
58typedef uint16_t RegIndex;
59
60// These enumerate all the registers for dependence tracking.
61enum DependenceTags {
62 FP_Base_DepTag = 32*3+9,
63 Ctrl_Base_DepTag = FP_Base_DepTag + 64,
64 Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs
65};
66
67// semantically meaningful register indices
68const int ZeroReg = 0; // architecturally meaningful
69// the rest of these depend on the ABI
70const int ReturnAddressReg = 31; // post call, precall is 15
71const int ReturnValueReg = 8; // Post return, 24 is pre-return.
72const int StackPointerReg = 14;
73const int FramePointerReg = 30;
74
75// Some OS syscall use a second register (o1) to return a second value
76const int SyscallPseudoReturnReg = 9;
77
78const int NumIntArchRegs = 32;
79const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
80
81const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
82
83} // namespace SparcISA
84
85#endif