nativetrace.cc (6388:4ace94e801cb) | nativetrace.cc (7678:f19b6a3a8cec) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 * Authors: Gabe Black 29 */ 30 31#include "arch/sparc/isa_traits.hh" 32#include "arch/sparc/registers.hh" 33#include "arch/sparc/nativetrace.hh" 34#include "cpu/thread_context.hh" 35#include "params/SparcNativeTrace.hh" | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 * Authors: Gabe Black 29 */ 30 31#include "arch/sparc/isa_traits.hh" 32#include "arch/sparc/registers.hh" 33#include "arch/sparc/nativetrace.hh" 34#include "cpu/thread_context.hh" 35#include "params/SparcNativeTrace.hh" |
36#include "sim/byteswap.hh" |
|
36 37namespace Trace { 38 39static const char *intRegNames[SparcISA::NumIntArchRegs] = { 40 //Global registers 41 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 42 //Output registers 43 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7", --- 55 unchanged lines hidden --- | 37 38namespace Trace { 39 40static const char *intRegNames[SparcISA::NumIntArchRegs] = { 41 //Global registers 42 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 43 //Output registers 44 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7", --- 55 unchanged lines hidden --- |