includes.isa (12334:e0ab29a34764) | includes.isa (12386:2bf5fb25a5f1) |
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1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 66 unchanged lines hidden (view full) --- 75output exec {{ 76#include "base/fenv.hh" 77 78#include <cmath> 79#include <limits> 80 81#include "arch/generic/memhelpers.hh" 82#include "arch/sparc/asi.hh" | 1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 66 unchanged lines hidden (view full) --- 75output exec {{ 76#include "base/fenv.hh" 77 78#include <cmath> 79#include <limits> 80 81#include "arch/generic/memhelpers.hh" 82#include "arch/sparc/asi.hh" |
83#include "base/bigint.hh" | |
84#include "cpu/base.hh" 85#include "cpu/exetrace.hh" 86#include "debug/Sparc.hh" 87#include "mem/packet.hh" 88#include "mem/packet_access.hh" 89#include "sim/full_system.hh" 90#include "sim/pseudo_inst.hh" 91#include "sim/sim_exit.hh" 92 93using namespace SparcISA; 94using namespace std; 95}}; 96 | 83#include "cpu/base.hh" 84#include "cpu/exetrace.hh" 85#include "debug/Sparc.hh" 86#include "mem/packet.hh" 87#include "mem/packet_access.hh" 88#include "sim/full_system.hh" 89#include "sim/pseudo_inst.hh" 90#include "sim/sim_exit.hh" 91 92using namespace SparcISA; 93using namespace std; 94}}; 95 |