1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 22 unchanged lines hidden (view full) --- 31//////////////////////////////////////////////////////////////////// 32// 33// Output include file directives. 34// 35 36output header {{ 37#include <sstream> 38#include <iostream> |
39 40#include "cpu/static_inst.hh" 41#include "arch/sparc/faults.hh" 42#include "mem/request.hh" // some constructors use MemReq flags 43#include "arch/sparc/isa_traits.hh" 44#include "arch/sparc/regfile.hh" 45}}; 46 47output decoder {{ 48#include "base/cprintf.hh" 49#include "base/loader/symtab.hh" 50#include "cpu/thread_context.hh" // for Jump::branchTarget() 51 |
52#if defined(linux) 53#include <fenv.h> 54#endif 55 56using namespace SparcISA; 57}}; 58 59output exec {{ |
60#if defined(linux) 61#include <fenv.h> 62#endif 63 |
64#include "cpu/base.hh" 65#include "cpu/exetrace.hh" 66#include "sim/sim_exit.hh" 67 68using namespace SparcISA; 69}}; 70 |