1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#ifndef __SPARC_FAULTS_HH__
33#define __SPARC_FAULTS_HH__
34
35#include "cpu/static_inst.hh"
36#include "sim/faults.hh"
37
38// The design of the "name" and "vect" functions is in sim/faults.hh
39
40namespace SparcISA
41{
42
43typedef uint32_t TrapType;
44typedef uint32_t FaultPriority;
45
46class ITB;
47
48class SparcFaultBase : public FaultBase
49{
50 public:
51 enum PrivilegeLevel
52 {
53 U, User = U,
54 P, Privileged = P,
55 H, Hyperprivileged = H,
56 NumLevels,
57 SH = -1,
58 ShouldntHappen = SH
59 };
60 struct FaultVals
61 {
62 const FaultName name;
63 const TrapType trapType;
64 const FaultPriority priority;
65 const PrivilegeLevel nextPrivilegeLevel[NumLevels];
66 FaultStat count;
67 };
68 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
69 StaticInst::nullStaticInstPtr);
70 virtual TrapType trapType() = 0;
71 virtual FaultPriority priority() = 0;
72 virtual FaultStat & countStat() = 0;
73 virtual PrivilegeLevel getNextLevel(PrivilegeLevel current) = 0;
74};
75
76template<typename T>
77class SparcFault : public SparcFaultBase
78{
79 protected:
80 static FaultVals vals;
81 public:
82 FaultName name() const { return vals.name; }
83 TrapType trapType() { return vals.trapType; }
84 FaultPriority priority() { return vals.priority; }
85 FaultStat & countStat() { return vals.count; }
86
87 PrivilegeLevel
88 getNextLevel(PrivilegeLevel current)
89 {
90 return vals.nextPrivilegeLevel[current];
91 }
92};
93
94class PowerOnReset : public SparcFault<PowerOnReset>
95{
96 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
97 StaticInst::nullStaticInstPtr);
98};
99
100class WatchDogReset : public SparcFault<WatchDogReset> {};
101
102class ExternallyInitiatedReset : public SparcFault<ExternallyInitiatedReset> {};
103
104class SoftwareInitiatedReset : public SparcFault<SoftwareInitiatedReset> {};
105
106class REDStateException : public SparcFault<REDStateException> {};
107
108class StoreError : public SparcFault<StoreError> {};
109
110class InstructionAccessException : public SparcFault<InstructionAccessException> {};
111
112// class InstructionAccessMMUMiss : public SparcFault<InstructionAccessMMUMiss> {};
113
114class InstructionAccessError : public SparcFault<InstructionAccessError> {};
115
116class IllegalInstruction : public SparcFault<IllegalInstruction> {};
117
118class PrivilegedOpcode : public SparcFault<PrivilegedOpcode> {};
119
120// class UnimplementedLDD : public SparcFault<UnimplementedLDD> {};
121
122// class UnimplementedSTD : public SparcFault<UnimplementedSTD> {};
123
124class FpDisabled : public SparcFault<FpDisabled> {};
125class VecDisabled : public SparcFault<VecDisabled> {};
126
127class FpExceptionIEEE754 : public SparcFault<FpExceptionIEEE754> {};
128
129class FpExceptionOther : public SparcFault<FpExceptionOther> {};
130
131class TagOverflow : public SparcFault<TagOverflow> {};
132
133class CleanWindow : public SparcFault<CleanWindow> {};
134
135class DivisionByZero : public SparcFault<DivisionByZero> {};
136
137class InternalProcessorError :
138 public SparcFault<InternalProcessorError> {};
139
140class InstructionInvalidTSBEntry :
141 public SparcFault<InstructionInvalidTSBEntry> {};
142
143class DataInvalidTSBEntry : public SparcFault<DataInvalidTSBEntry> {};
144
145class DataAccessException : public SparcFault<DataAccessException> {};
146
147// class DataAccessMMUMiss : public SparcFault<DataAccessMMUMiss> {};
148
149class DataAccessError : public SparcFault<DataAccessError> {};
150
151class DataAccessProtection : public SparcFault<DataAccessProtection> {};
152
153class MemAddressNotAligned :
154 public SparcFault<MemAddressNotAligned> {};
155
156class LDDFMemAddressNotAligned : public SparcFault<LDDFMemAddressNotAligned> {};
157
158class STDFMemAddressNotAligned : public SparcFault<STDFMemAddressNotAligned> {};
159
160class PrivilegedAction : public SparcFault<PrivilegedAction> {};
161
162class LDQFMemAddressNotAligned : public SparcFault<LDQFMemAddressNotAligned> {};
163
164class STQFMemAddressNotAligned : public SparcFault<STQFMemAddressNotAligned> {};
165
166class InstructionRealTranslationMiss :
167 public SparcFault<InstructionRealTranslationMiss> {};
168
169class DataRealTranslationMiss : public SparcFault<DataRealTranslationMiss> {};
170
171// class AsyncDataError : public SparcFault<AsyncDataError> {};
172
173template <class T>
174class EnumeratedFault : public SparcFault<T>
175{
176 protected:
177 uint32_t _n;
178 public:
179 EnumeratedFault(uint32_t n) : SparcFault<T>(), _n(n) {}
180 TrapType trapType() { return SparcFault<T>::trapType() + _n; }
181};
182
183class InterruptLevelN : public EnumeratedFault<InterruptLevelN>
184{
185 public:
186 InterruptLevelN(uint32_t n) : EnumeratedFault<InterruptLevelN>(n) {;}
187 FaultPriority priority() { return 3200 - _n*100; }
188};
189
190class HstickMatch : public SparcFault<HstickMatch> {};
191
192class TrapLevelZero : public SparcFault<TrapLevelZero> {};
193
194class InterruptVector : public SparcFault<InterruptVector> {};
195
196class PAWatchpoint : public SparcFault<PAWatchpoint> {};
197
198class VAWatchpoint : public SparcFault<VAWatchpoint> {};
199
200class FastInstructionAccessMMUMiss :
201 public SparcFault<FastInstructionAccessMMUMiss>
202{
203 protected:
204 Addr vaddr;
205 public:
206 FastInstructionAccessMMUMiss(Addr addr) : vaddr(addr)
207 {}
208 FastInstructionAccessMMUMiss() : vaddr(0)
209 {}
210 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
211 StaticInst::nullStaticInstPtr);
212};
213
214class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
215{
216 protected:
217 Addr vaddr;
218 public:
219 FastDataAccessMMUMiss(Addr addr) : vaddr(addr)
220 {}
221 FastDataAccessMMUMiss() : vaddr(0)
222 {}
223 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
224 StaticInst::nullStaticInstPtr);
225};
226
227class FastDataAccessProtection : public SparcFault<FastDataAccessProtection> {};
228
229class InstructionBreakpoint : public SparcFault<InstructionBreakpoint> {};
230
231class CpuMondo : public SparcFault<CpuMondo> {};
232
233class DevMondo : public SparcFault<DevMondo> {};
234
235class ResumableError : public SparcFault<ResumableError> {};
236
237class SpillNNormal : public EnumeratedFault<SpillNNormal>
238{
239 public:
240 SpillNNormal(uint32_t n) : EnumeratedFault<SpillNNormal>(n) {;}
241 // These need to be handled specially to enable spill traps in SE
242 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
243 StaticInst::nullStaticInstPtr);
244};
245
246class SpillNOther : public EnumeratedFault<SpillNOther>
247{
248 public:
249 SpillNOther(uint32_t n) : EnumeratedFault<SpillNOther>(n)
250 {}
251};
252
253class FillNNormal : public EnumeratedFault<FillNNormal>
254{
255 public:
256 FillNNormal(uint32_t n) : EnumeratedFault<FillNNormal>(n)
257 {}
258 // These need to be handled specially to enable fill traps in SE
259 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
260 StaticInst::nullStaticInstPtr);
261};
262
263class FillNOther : public EnumeratedFault<FillNOther>
264{
265 public:
266 FillNOther(uint32_t n) : EnumeratedFault<FillNOther>(n)
267 {}
268};
269
270class TrapInstruction : public EnumeratedFault<TrapInstruction>
271{
272 public:
273 TrapInstruction(uint32_t n) : EnumeratedFault<TrapInstruction>(n)
274 {}
275 // In SE, trap instructions are requesting services from the OS.
276 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
277 StaticInst::nullStaticInstPtr);
278};
279
280/*
281 * Explicitly declare template static member variables to avoid warnings
282 * in some clang versions
283 */
284template<> SparcFaultBase::FaultVals SparcFault<PowerOnReset>::vals;
285template<> SparcFaultBase::FaultVals SparcFault<WatchDogReset>::vals;
286template<> SparcFaultBase::FaultVals
287 SparcFault<ExternallyInitiatedReset>::vals;
288template<> SparcFaultBase::FaultVals SparcFault<SoftwareInitiatedReset>::vals;
289template<> SparcFaultBase::FaultVals SparcFault<REDStateException>::vals;
290template<> SparcFaultBase::FaultVals SparcFault<StoreError>::vals;
291template<> SparcFaultBase::FaultVals
292 SparcFault<InstructionAccessException>::vals;
293template<> SparcFaultBase::FaultVals SparcFault<InstructionAccessError>::vals;
294template<> SparcFaultBase::FaultVals SparcFault<IllegalInstruction>::vals;
295template<> SparcFaultBase::FaultVals SparcFault<PrivilegedOpcode>::vals;
296template<> SparcFaultBase::FaultVals SparcFault<FpDisabled>::vals;
297template<> SparcFaultBase::FaultVals SparcFault<VecDisabled>::vals;
298template<> SparcFaultBase::FaultVals SparcFault<FpExceptionIEEE754>::vals;
299template<> SparcFaultBase::FaultVals SparcFault<FpExceptionOther>::vals;
300template<> SparcFaultBase::FaultVals SparcFault<TagOverflow>::vals;
301template<> SparcFaultBase::FaultVals SparcFault<CleanWindow>::vals;
302template<> SparcFaultBase::FaultVals SparcFault<DivisionByZero>::vals;
303template<> SparcFaultBase::FaultVals SparcFault<InternalProcessorError>::vals;
304template<> SparcFaultBase::FaultVals
305 SparcFault<InstructionInvalidTSBEntry>::vals;
306template<> SparcFaultBase::FaultVals SparcFault<DataInvalidTSBEntry>::vals;
307template<> SparcFaultBase::FaultVals SparcFault<DataAccessException>::vals;
308template<> SparcFaultBase::FaultVals SparcFault<DataAccessError>::vals;
309template<> SparcFaultBase::FaultVals SparcFault<DataAccessProtection>::vals;
310template<> SparcFaultBase::FaultVals SparcFault<MemAddressNotAligned>::vals;
311template<> SparcFaultBase::FaultVals
312 SparcFault<LDDFMemAddressNotAligned>::vals;
313template<> SparcFaultBase::FaultVals
314 SparcFault<STDFMemAddressNotAligned>::vals;
315template<> SparcFaultBase::FaultVals SparcFault<PrivilegedAction>::vals;
316template<> SparcFaultBase::FaultVals
317 SparcFault<LDQFMemAddressNotAligned>::vals;
318template<> SparcFaultBase::FaultVals
319 SparcFault<STQFMemAddressNotAligned>::vals;
320template<> SparcFaultBase::FaultVals
321 SparcFault<InstructionRealTranslationMiss>::vals;
322template<> SparcFaultBase::FaultVals SparcFault<DataRealTranslationMiss>::vals;
323template<> SparcFaultBase::FaultVals SparcFault<InterruptLevelN>::vals;
324template<> SparcFaultBase::FaultVals SparcFault<HstickMatch>::vals;
325template<> SparcFaultBase::FaultVals SparcFault<TrapLevelZero>::vals;
326template<> SparcFaultBase::FaultVals SparcFault<InterruptVector>::vals;
327template<> SparcFaultBase::FaultVals SparcFault<PAWatchpoint>::vals;
328template<> SparcFaultBase::FaultVals SparcFault<VAWatchpoint>::vals;
329template<> SparcFaultBase::FaultVals
330 SparcFault<FastInstructionAccessMMUMiss>::vals;
331template<> SparcFaultBase::FaultVals SparcFault<FastDataAccessMMUMiss>::vals;
332template<>
333 SparcFaultBase::FaultVals SparcFault<FastDataAccessProtection>::vals;
334template<> SparcFaultBase::FaultVals SparcFault<InstructionBreakpoint>::vals;
335template<> SparcFaultBase::FaultVals SparcFault<CpuMondo>::vals;
336template<> SparcFaultBase::FaultVals SparcFault<DevMondo>::vals;
337template<> SparcFaultBase::FaultVals SparcFault<ResumableError>::vals;
338template<> SparcFaultBase::FaultVals SparcFault<SpillNNormal>::vals;
339template<> SparcFaultBase::FaultVals SparcFault<SpillNOther>::vals;
340template<> SparcFaultBase::FaultVals SparcFault<FillNNormal>::vals;
341template<> SparcFaultBase::FaultVals SparcFault<FillNOther>::vals;
342template<> SparcFaultBase::FaultVals SparcFault<TrapInstruction>::vals;
343
344
345void enterREDState(ThreadContext *tc);
346
347void doREDFault(ThreadContext *tc, TrapType tt);
348
349void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv);
350
351void getREDVector(MiscReg TT, Addr &PC, Addr &NPC);
352
353void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT);
354
355void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT,
356 MiscReg TL);
357
358} // namespace SparcISA
359
360#endif // __SPARC_FAULTS_HH__