1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 18 unchanged lines hidden (view full) ---

27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#ifndef __SPARC_FAULTS_HH__
33#define __SPARC_FAULTS_HH__
34
35#include "config/full_system.hh"
36#include "sim/faults.hh"
37
38// The design of the "name" and "vect" functions is in sim/faults.hh
39
40namespace SparcISA
41{
42
43typedef uint32_t TrapType;
44typedef uint32_t FaultPriority;
45
46class ITB;
47
48class SparcFaultBase : public FaultBase
49{
50 public:
51 enum PrivilegeLevel
52 {
53 U, User = U,
54 P, Privileged = P,
55 H, Hyperprivileged = H,

--- 141 unchanged lines hidden (view full) ---

197
198class InterruptVector : public SparcFault<InterruptVector> {};
199
200class PAWatchpoint : public SparcFault<PAWatchpoint> {};
201
202class VAWatchpoint : public SparcFault<VAWatchpoint> {};
203
204class FastInstructionAccessMMUMiss :
205 public SparcFault
206{
207#if !FULL_SYSTEM
208 protected:
209 Addr vaddr;
210 public:
211 FastInstructionAccessMMUMiss(Addr addr) : vaddr(addr)
212 {}
213 void invoke(ThreadContext * tc);
214#endif
215};
216
217class FastDataAccessMMUMiss : public SparcFault
218{
219#if !FULL_SYSTEM
220 protected:
221 Addr vaddr;
222 public:
223 FastDataAccessMMUMiss(Addr addr) : vaddr(addr)
224 {}
225 void invoke(ThreadContext * tc);
226#endif
227};
228
229class FastDataAccessProtection : public SparcFault<FastDataAccessProtection> {};
230
231class InstructionBreakpoint : public SparcFault<InstructionBreakpoint> {};
232
233class CpuMondo : public SparcFault<CpuMondo> {};
234
235class DevMondo : public SparcFault<DevMondo> {};

--- 59 unchanged lines hidden ---