decoder.hh (9022:bb25e7646c41) decoder.hh (9023:e9201a7bce59)
1/*
2 * Copyright (c) 2012 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 17 unchanged lines hidden (view full) ---

26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_DECODER_HH__
32#define __ARCH_SPARC_DECODER_HH__
33
1/*
2 * Copyright (c) 2012 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 17 unchanged lines hidden (view full) ---

26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_DECODER_HH__
32#define __ARCH_SPARC_DECODER_HH__
33
34#include "arch/sparc/registers.hh"
34#include "arch/types.hh"
35#include "cpu/decode_cache.hh"
36#include "cpu/static_inst_fwd.hh"
35#include "arch/types.hh"
36#include "cpu/decode_cache.hh"
37#include "cpu/static_inst_fwd.hh"
38#include "cpu/thread_context.hh"
37
39
40class ThreadContext;
41
38namespace SparcISA
39{
40
41class Decoder
42{
43 protected:
42namespace SparcISA
43{
44
45class Decoder
46{
47 protected:
48 ThreadContext * tc;
49 // The extended machine instruction being generated
50 ExtMachInst emi;
51 bool instDone;
52
53 public:
54 Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
55 {}
56
57 ThreadContext *
58 getTC()
59 {
60 return tc;
61 }
62
63 void
64 setTC(ThreadContext * _tc)
65 {
66 tc = _tc;
67 }
68
69 void process() {}
70
71 void
72 reset()
73 {
74 instDone = false;
75 }
76
77 // Use this to give data to the predecoder. This should be used
78 // when there is control flow.
79 void
80 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
81 {
82 emi = inst;
83 // The I bit, bit 13, is used to figure out where the ASI
84 // should come from. Use that in the ExtMachInst. This is
85 // slightly redundant, but it removes the need to put a condition
86 // into all the execute functions
87 if (inst & (1 << 13)) {
88 emi |= (static_cast<ExtMachInst>(
89 tc->readMiscRegNoEffect(MISCREG_ASI))
90 << (sizeof(MachInst) * 8));
91 } else {
92 emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
93 << (sizeof(MachInst) * 8));
94 }
95 instDone = true;
96 }
97
98 bool
99 needMoreBytes()
100 {
101 return true;
102 }
103
104 bool
105 instReady()
106 {
107 return instDone;
108 }
109
110 protected:
44 /// A cache of decoded instruction objects.
45 static DecodeCache defaultCache;
46
47 public:
48 StaticInstPtr decodeInst(ExtMachInst mach_inst);
49
50 /// Decode a machine instruction.
51 /// @param mach_inst The binary instruction to decode.
52 /// @retval A pointer to the corresponding StaticInst object.
53 StaticInstPtr
54 decode(ExtMachInst mach_inst, Addr addr)
55 {
56 return defaultCache.decode(this, mach_inst, addr);
57 }
111 /// A cache of decoded instruction objects.
112 static DecodeCache defaultCache;
113
114 public:
115 StaticInstPtr decodeInst(ExtMachInst mach_inst);
116
117 /// Decode a machine instruction.
118 /// @param mach_inst The binary instruction to decode.
119 /// @retval A pointer to the corresponding StaticInst object.
120 StaticInstPtr
121 decode(ExtMachInst mach_inst, Addr addr)
122 {
123 return defaultCache.decode(this, mach_inst, addr);
124 }
125
126 StaticInstPtr
127 decode(SparcISA::PCState &nextPC)
128 {
129 if (!instDone)
130 return NULL;
131 instDone = false;
132 return decode(emi, nextPC.instAddr());
133 }
58};
59
60} // namespace SparcISA
61
62#endif // __ARCH_SPARC_DECODER_HH__
134};
135
136} // namespace SparcISA
137
138#endif // __ARCH_SPARC_DECODER_HH__