1/*
2 * Copyright (c) 2012 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_DECODER_HH__
32#define __ARCH_SPARC_DECODER_HH__
33
34#include "arch/generic/decode_cache.hh"
35#include "arch/sparc/registers.hh"
36#include "arch/types.hh"
37#include "cpu/static_inst.hh"
38
39namespace SparcISA
40{
41
42class Decoder
43{
44 protected:
45 // The extended machine instruction being generated
46 ExtMachInst emi;
47 bool instDone;
48 MiscReg asi;
49
50 public:
51 Decoder() : instDone(false), asi(0)
52 {}
53
54 void process() {}
55
56 void
57 reset()
58 {
59 instDone = false;
60 }
61
62 // Use this to give data to the predecoder. This should be used
63 // when there is control flow.
64 void
65 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
66 {
67 emi = inst;
68 // The I bit, bit 13, is used to figure out where the ASI
69 // should come from. Use that in the ExtMachInst. This is
70 // slightly redundant, but it removes the need to put a condition
71 // into all the execute functions
72 if (inst & (1 << 13)) {
73 emi |= (static_cast<ExtMachInst>(
74 asi << (sizeof(MachInst) * 8)));
75 } else {
76 emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
77 << (sizeof(MachInst) * 8));
78 }
79 instDone = true;
80 }
81
82 bool
83 needMoreBytes()
84 {
85 return true;
86 }
87
88 bool
89 instReady()
90 {
91 return instDone;
92 }
93
94 void
95 setContext(MiscReg _asi)
96 {
97 asi = _asi;
98 }
99
| 1/*
2 * Copyright (c) 2012 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_DECODER_HH__
32#define __ARCH_SPARC_DECODER_HH__
33
34#include "arch/generic/decode_cache.hh"
35#include "arch/sparc/registers.hh"
36#include "arch/types.hh"
37#include "cpu/static_inst.hh"
38
39namespace SparcISA
40{
41
42class Decoder
43{
44 protected:
45 // The extended machine instruction being generated
46 ExtMachInst emi;
47 bool instDone;
48 MiscReg asi;
49
50 public:
51 Decoder() : instDone(false), asi(0)
52 {}
53
54 void process() {}
55
56 void
57 reset()
58 {
59 instDone = false;
60 }
61
62 // Use this to give data to the predecoder. This should be used
63 // when there is control flow.
64 void
65 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
66 {
67 emi = inst;
68 // The I bit, bit 13, is used to figure out where the ASI
69 // should come from. Use that in the ExtMachInst. This is
70 // slightly redundant, but it removes the need to put a condition
71 // into all the execute functions
72 if (inst & (1 << 13)) {
73 emi |= (static_cast<ExtMachInst>(
74 asi << (sizeof(MachInst) * 8)));
75 } else {
76 emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
77 << (sizeof(MachInst) * 8));
78 }
79 instDone = true;
80 }
81
82 bool
83 needMoreBytes()
84 {
85 return true;
86 }
87
88 bool
89 instReady()
90 {
91 return instDone;
92 }
93
94 void
95 setContext(MiscReg _asi)
96 {
97 asi = _asi;
98 }
99
|
100 protected:
101 /// A cache of decoded instruction objects.
102 static GenericISA::BasicDecodeCache defaultCache;
103
104 public:
105 StaticInstPtr decodeInst(ExtMachInst mach_inst);
106
107 /// Decode a machine instruction.
108 /// @param mach_inst The binary instruction to decode.
109 /// @retval A pointer to the corresponding StaticInst object.
110 StaticInstPtr
111 decode(ExtMachInst mach_inst, Addr addr)
112 {
113 return defaultCache.decode(this, mach_inst, addr);
114 }
115
116 StaticInstPtr
117 decode(SparcISA::PCState &nextPC)
118 {
119 if (!instDone)
120 return NULL;
121 instDone = false;
122 return decode(emi, nextPC.instAddr());
123 }
124};
125
126} // namespace SparcISA
127
128#endif // __ARCH_SPARC_DECODER_HH__
| 102 protected:
103 /// A cache of decoded instruction objects.
104 static GenericISA::BasicDecodeCache defaultCache;
105
106 public:
107 StaticInstPtr decodeInst(ExtMachInst mach_inst);
108
109 /// Decode a machine instruction.
110 /// @param mach_inst The binary instruction to decode.
111 /// @retval A pointer to the corresponding StaticInst object.
112 StaticInstPtr
113 decode(ExtMachInst mach_inst, Addr addr)
114 {
115 return defaultCache.decode(this, mach_inst, addr);
116 }
117
118 StaticInstPtr
119 decode(SparcISA::PCState &nextPC)
120 {
121 if (!instDone)
122 return NULL;
123 instDone = false;
124 return decode(emi, nextPC.instAddr());
125 }
126};
127
128} // namespace SparcISA
129
130#endif // __ARCH_SPARC_DECODER_HH__
|