1/*
2 * Copyright (c) 2012 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
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34#include "arch/generic/decode_cache.hh"
35#include "arch/sparc/registers.hh"
36#include "arch/types.hh"
37#include "cpu/static_inst.hh"
38
39namespace SparcISA
40{
41
42class Decoder
43{
44 protected:
45 // The extended machine instruction being generated
46 ExtMachInst emi;
47 bool instDone;
48 MiscReg asi;
49
50 public:
51 Decoder() : instDone(false), asi(0)
52 {}
53
54 void process() {}
55
56 void
57 reset()
58 {
59 instDone = false;
--- 71 unchanged lines hidden ---
2 * Copyright (c) 2012 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
--- 25 unchanged lines hidden (view full) ---
34#include "arch/generic/decode_cache.hh"
35#include "arch/sparc/registers.hh"
36#include "arch/types.hh"
37#include "cpu/static_inst.hh"
38
39namespace SparcISA
40{
41
42class Decoder
43{
44 protected:
45 // The extended machine instruction being generated
46 ExtMachInst emi;
47 bool instDone;
48 MiscReg asi;
49
50 public:
51 Decoder() : instDone(false), asi(0)
52 {}
53
54 void process() {}
55
56 void
57 reset()
58 {
59 instDone = false;
--- 71 unchanged lines hidden ---