asi.hh (4191:c191c1fec061) asi.hh (7741:340b6f01d69b)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 20 unchanged lines hidden (view full) ---

29 * Ali Saidi
30 */
31
32#ifndef __ARCH_SPARC_ASI_HH__
33#define __ARCH_SPARC_ASI_HH__
34
35namespace SparcISA
36{
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 20 unchanged lines hidden (view full) ---

29 * Ali Saidi
30 */
31
32#ifndef __ARCH_SPARC_ASI_HH__
33#define __ARCH_SPARC_ASI_HH__
34
35namespace SparcISA
36{
37 enum ASI {
38 ASI_IMPLICIT = 0x00,
39 /* Priveleged ASIs */
40 //0x00-0x03 implementation dependent
41 ASI_NUCLEUS = 0x4,
42 ASI_N = 0x4,
43 //0x05-0x0B implementation dependent
44 ASI_NL = 0xC,
45 ASI_NUCLEUS_LITTLE = ASI_NL,
46 //0x0D-0x0F implementation dependent
47 ASI_AIUP = 0x10,
48 ASI_AS_IF_USER_PRIMARY = ASI_AIUP,
49 ASI_AIUS = 0x11,
50 ASI_AS_IF_USER_SECONDARY = ASI_AIUS,
51 //0x12-0x13 implementation dependent
52 ASI_REAL = 0x14,
53 ASI_REAL_IO = 0x15,
54 ASI_BLK_AIUP = 0x16,
55 ASI_BLOCK_AS_IF_USER_PRIMARY = ASI_BLK_AIUP,
56 ASI_BLK_AIUS = 0x17,
57 ASI_BLOCK_AS_IF_USER_SECONDARY = ASI_BLK_AIUS,
58 ASI_AIUP_L = 0x18,
59 ASI_AS_IF_USER_PRIMARY_LITTLE = ASI_AIUP_L,
60 ASI_AIUS_L = 0x19,
61 ASI_AS_IF_USER_SECONDARY_LITTLE = ASI_AIUS_L,
62 //0x1A-0x1B implementation dependent
63 ASI_REAL_L = 0x1C,
64 ASI_REAL_LITTLE = ASI_REAL_L,
65 ASI_REAL_IO_L = 0x1D,
66 ASI_REAL_IO_LITTLE = ASI_REAL_IO_L,
67 ASI_BLK_AIUP_L = 0x1E,
68 ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = ASI_BLK_AIUP_L,
69 ASI_BLK_AIUS_L = 0x1F,
70 ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = ASI_BLK_AIUS_L,
71 ASI_SCRATCHPAD = 0x20,
72 ASI_MMU = 0x21,
73 ASI_LDTX_AIUP = 0x22,
74 ASI_LD_TWINX_AS_IF_USER_PRIMARY = ASI_LDTX_AIUP,
75 ASI_LDTX_AIUS = 0x23,
76 ASI_LD_TWINX_AS_IF_USER_SECONDARY = ASI_LDTX_AIUS,
77 ASI_QUAD_LDD = 0x24,
78 ASI_QUEUE = 0x25,
79 ASI_QUAD_LDD_REAL = 0x26,
80 ASI_LDTX_REAL = ASI_QUAD_LDD_REAL,
81 ASI_LDTX_N = 0x27,
82 ASI_LD_TWINX_NUCLEUS = ASI_LDTX_N,
83 ASI_ST_BLKINIT_NUCLEUS = ASI_LDTX_N,
84 ASI_STBI_N = ASI_LDTX_N,
85 //0x28-0x29 implementation dependent
86 ASI_LDTX_AIUP_L = 0x2A,
87 ASI_TWINX_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
88 ASI_ST_BLKINIT_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
89 ASI_STBI_AIUP_L = ASI_LDTX_AIUP_L,
90 ASI_LDTX_AIUS_L = 0x2B,
91 ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
92 ASI_ST_BLKINIT_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
93 ASI_STBI_AIUS_L = ASI_LDTX_AIUS_L,
94 ASI_LTX_L = 0x2C,
95 ASI_TWINX_LITTLE = ASI_LTX_L,
96 //0x2D implementation dependent
97 ASI_LDTX_REAL_L = 0x2E,
98 ASI_LD_TWINX_REAL_LITTLE = ASI_LDTX_REAL_L,
99 ASI_LDTX_NL = 0x2F,
100 ASI_LD_TWINX_NUCLEUS_LITTLE = ASI_LDTX_NL,
101 //0x20 implementation dependent
102 ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x31,
103 ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x32,
104 ASI_DMMU_CTXT_ZERO_CONFIG = 0x33,
105 //0x34 implementation dependent
106 ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x35,
107 ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x36,
108 ASI_IMMU_CTXT_ZERO_CONFIG = 0x37,
109 //0x38 implementation dependent
110 ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x39,
111 ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3A,
112 ASI_DMMU_CTXT_NONZERO_CONFIG = 0x3B,
113 //0x3C implementation dependent
114 ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x3D,
115 ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3E,
116 ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F,
117 ASI_STREAM_MA = 0x40,
118 ASI_CMT_SHARED = 0x41,
119 //0x41 implementation dependent
120 ASI_SPARC_BIST_CONTROL = 0x42,
121 ASI_INST_MASK_REG = 0x42,
122 ASI_LSU_DIAG_REG = 0x42,
123 //0x43 implementation dependent
124 ASI_STM_CTL_REG = 0x44,
125 ASI_LSU_CONTROL_REG = 0x45,
126 ASI_DCACHE_DATA = 0x46,
127 ASI_DCACHE_TAG = 0x47,
128 ASI_INTR_DISPATCH_STATUS = 0x48,
129 ASI_INTR_RECEIVE = 0x49,
130 ASI_UPA_CONFIG_REGISTER = 0x4A,
131 ASI_SPARC_ERROR_EN_REG = 0x4B,
132 ASI_SPARC_ERROR_STATUS_REG = 0x4C,
133 ASI_SPARC_ERROR_ADDRESS_REG = 0x4D,
134 ASI_ECACHE_TAG_DATA = 0x4E,
135 ASI_HYP_SCRATCHPAD = 0x4F,
136 ASI_IMMU = 0x50,
137 ASI_IMMU_TSB_PS0_PTR_REG = 0x51,
138 ASI_IMMU_TSB_PS1_PTR_REG = 0x52,
139 //0x53 implementation dependent
140 ASI_ITLB_DATA_IN_REG = 0x54,
141 ASI_ITLB_DATA_ACCESS_REG = 0x55,
142 ASI_ITLB_TAG_READ_REG = 0x56,
143 ASI_IMMU_DEMAP = 0x57,
144 ASI_DMMU = 0x58,
145 ASI_DMMU_TSB_PS0_PTR_REG = 0x59,
146 ASI_DMMU_TSB_PS1_PTR_REG = 0x5A,
147 ASI_DMMU_TSB_DIRECT_PTR_REG = 0x5B,
148 ASI_DTLB_DATA_IN_REG = 0x5C,
149 ASI_DTLB_DATA_ACCESS_REG = 0x5D,
150 ASI_DTLB_TAG_READ_REG = 0x5E,
151 ASI_DMMU_DEMAP = 0x5F,
152 ASI_TLB_INVALIDATE_ALL = 0x60,
153 //0x61-0x62 implementation dependent
154 ASI_CMT_PER_STRAND = 0x63,
155 //0x64-0x65 implementation dependent
156 ASI_ICACHE_INSTR = 0x66,
157 ASI_ICACHE_TAG = 0x67,
158 //0x68-0x71 implementation dependent
159 ASI_SWVR_INTR_RECEIVE = 0x72,
160 ASI_SWVR_UDB_INTR_W = 0x73,
161 ASI_SWVR_UDB_INTR_R = 0x74,
162 //0x74-0x7F reserved
163 /* Unpriveleged ASIs */
164 ASI_P = 0x80,
165 ASI_PRIMARY = ASI_P,
166 ASI_S = 0x81,
167 ASI_SECONDARY = ASI_S,
168 ASI_PNF = 0x82,
169 ASI_PRIMARY_NO_FAULT = ASI_PNF,
170 ASI_SNF = 0x83,
171 ASI_SECONDARY_NO_FAULT = ASI_SNF,
172 //0x84-0x87 reserved
173 ASI_PL = 0x88,
174 ASI_PRIMARY_LITTLE = ASI_PL,
175 ASI_SL = 0x89,
176 ASI_SECONDARY_LITTLE = ASI_SL,
177 ASI_PNFL = 0x8A,
178 ASI_PRIMARY_NO_FAULT_LITTLE = ASI_PNFL,
179 ASI_SNFL = 0x8B,
180 ASI_SECONDARY_NO_FAULT_LITTLE = ASI_SNFL,
181 //0x8C-0xBF reserved
182 ASI_PST8_P = 0xC0,
183 ASI_PST8_PRIMARY = ASI_PST8_P,
184 ASI_PST8_S = 0xC1,
185 ASI_PST8_SECONDARY = ASI_PST8_S,
186 ASI_PST16_P = 0xC2,
187 ASI_PST16_PRIMARY = ASI_PST16_P,
188 ASI_PST16_S = 0xC3,
189 ASI_PST16_SECONDARY = ASI_PST16_S,
190 ASI_PST32_P = 0xC4,
191 ASI_PST32_PRIMARY = ASI_PST32_P,
192 ASI_PST32_S = 0xC5,
193 ASI_PST32_SECONDARY = ASI_PST32_S,
194 //0xC6-0xC7 implementation dependent
195 ASI_PST8_PL = 0xC8,
196 ASI_PST8_PRIMARY_LITTLE = ASI_PST8_PL,
197 ASI_PST8_SL = 0xC9,
198 ASI_PST8_SECONDARY_LITTLE = ASI_PST8_SL,
199 ASI_PST16_PL = 0xCA,
200 ASI_PST16_PRIMARY_LITTLE = ASI_PST16_PL,
201 ASI_PST16_SL = 0xCB,
202 ASI_PST16_SECONDARY_LITTLE = ASI_PST16_SL,
203 ASI_PST32_PL = 0xCC,
204 ASI_PST32_PRIMARY_LITTLE = ASI_PST32_PL,
205 ASI_PST32_SL = 0xCD,
206 ASI_PST32_SECONDARY_LITTLE = ASI_PST32_SL,
207 //0xCE-0xCF implementation dependent
208 ASI_FL8_P = 0xD0,
209 ASI_FL8_PRIMARY = ASI_FL8_P,
210 ASI_FL8_S = 0xD1,
211 ASI_FL8_SECONDARY = ASI_FL8_S,
212 ASI_FL16_P = 0xD2,
213 ASI_FL16_PRIMARY = ASI_FL16_P,
214 ASI_FL16_S = 0xD3,
215 ASI_FL16_SECONDARY = ASI_FL16_S,
216 //0xD4-0xD7 implementation dependent
217 ASI_FL8_PL = 0xD8,
218 ASI_FL8_PRIMARY_LITTLE = ASI_FL8_PL,
219 ASI_FL8_SL = 0xD9,
220 ASI_FL8_SECONDARY_LITTLE = ASI_FL8_SL,
221 ASI_FL16_PL = 0xDA,
222 ASI_FL16_PRIMARY_LITTLE = ASI_FL16_PL,
223 ASI_FL16_SL = 0xDB,
224 ASI_FL16_SECONDARY_LITTLE = ASI_FL16_SL,
225 //0xDC-0xDF implementation dependent
226 //0xE0-0xE1 reserved
227 ASI_LDTX_P = 0xE2,
228 ASI_LD_TWINX_PRIMARY = ASI_LDTX_P,
229 ASI_LDTX_S = 0xE3,
230 ASI_LD_TWINX_SECONDARY = ASI_LDTX_S,
231 //0xE4-0xE9 implementation dependent
232 ASI_LDTX_PL = 0xEA,
233 ASI_LD_TWINX_PRIMARY_LITTLE = ASI_LDTX_PL,
234 ASI_LDTX_SL = 0xEB,
235 ASI_LD_TWINX_SECONDARY_LITTLE = ASI_LDTX_SL,
236 //0xEC-0xEF implementation dependent
237 ASI_BLK_P = 0xF0,
238 ASI_BLOCK_PRIMARY = ASI_BLK_P,
239 ASI_BLK_S = 0xF1,
240 ASI_BLOCK_SECONDARY = ASI_BLK_S,
241 //0xF2-0xF7 implementation dependent
242 ASI_BLK_PL = 0xF8,
243 ASI_BLOCK_PRIMARY_LITTLE = ASI_BLK_PL,
244 ASI_BLK_SL = 0xF9,
245 ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL,
246 //0xFA-0xFF implementation dependent
247 MAX_ASI = 0xFF
248 };
249
37
250 //Functions that classify an asi
251 bool AsiIsBlock(ASI);
252 bool AsiIsPrimary(ASI);
253 bool AsiIsSecondary(ASI);
254 bool AsiIsNucleus(ASI);
255 bool AsiIsAsIfUser(ASI);
256 bool AsiIsIO(ASI);
257 bool AsiIsReal(ASI);
258 bool AsiIsLittle(ASI);
259 bool AsiIsTwin(ASI);
260 bool AsiIsPartialStore(ASI);
261 bool AsiIsFloatingLoad(ASI);
262 bool AsiIsNoFault(ASI);
263 bool AsiIsScratchPad(ASI);
264 bool AsiIsCmt(ASI);
265 bool AsiIsQueue(ASI);
266 bool AsiIsDtlb(ASI);
267 bool AsiIsMmu(ASI);
268 bool AsiIsUnPriv(ASI);
269 bool AsiIsPriv(ASI);
270 bool AsiIsHPriv(ASI);
271 bool AsiIsReg(ASI);
272 bool AsiIsInterrupt(ASI);
273 bool AsiIsSparcError(ASI);
38enum ASI {
39 ASI_IMPLICIT = 0x00,
40 /* Priveleged ASIs */
41 // 0x00-0x03 implementation dependent
42 ASI_NUCLEUS = 0x4,
43 ASI_N = 0x4,
44 // 0x05-0x0B implementation dependent
45 ASI_NL = 0xC,
46 ASI_NUCLEUS_LITTLE = ASI_NL,
47 // 0x0D-0x0F implementation dependent
48 ASI_AIUP = 0x10,
49 ASI_AS_IF_USER_PRIMARY = ASI_AIUP,
50 ASI_AIUS = 0x11,
51 ASI_AS_IF_USER_SECONDARY = ASI_AIUS,
52 // 0x12-0x13 implementation dependent
53 ASI_REAL = 0x14,
54 ASI_REAL_IO = 0x15,
55 ASI_BLK_AIUP = 0x16,
56 ASI_BLOCK_AS_IF_USER_PRIMARY = ASI_BLK_AIUP,
57 ASI_BLK_AIUS = 0x17,
58 ASI_BLOCK_AS_IF_USER_SECONDARY = ASI_BLK_AIUS,
59 ASI_AIUP_L = 0x18,
60 ASI_AS_IF_USER_PRIMARY_LITTLE = ASI_AIUP_L,
61 ASI_AIUS_L = 0x19,
62 ASI_AS_IF_USER_SECONDARY_LITTLE = ASI_AIUS_L,
63 // 0x1A-0x1B implementation dependent
64 ASI_REAL_L = 0x1C,
65 ASI_REAL_LITTLE = ASI_REAL_L,
66 ASI_REAL_IO_L = 0x1D,
67 ASI_REAL_IO_LITTLE = ASI_REAL_IO_L,
68 ASI_BLK_AIUP_L = 0x1E,
69 ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = ASI_BLK_AIUP_L,
70 ASI_BLK_AIUS_L = 0x1F,
71 ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = ASI_BLK_AIUS_L,
72 ASI_SCRATCHPAD = 0x20,
73 ASI_MMU = 0x21,
74 ASI_LDTX_AIUP = 0x22,
75 ASI_LD_TWINX_AS_IF_USER_PRIMARY = ASI_LDTX_AIUP,
76 ASI_LDTX_AIUS = 0x23,
77 ASI_LD_TWINX_AS_IF_USER_SECONDARY = ASI_LDTX_AIUS,
78 ASI_QUAD_LDD = 0x24,
79 ASI_QUEUE = 0x25,
80 ASI_QUAD_LDD_REAL = 0x26,
81 ASI_LDTX_REAL = ASI_QUAD_LDD_REAL,
82 ASI_LDTX_N = 0x27,
83 ASI_LD_TWINX_NUCLEUS = ASI_LDTX_N,
84 ASI_ST_BLKINIT_NUCLEUS = ASI_LDTX_N,
85 ASI_STBI_N = ASI_LDTX_N,
86 // 0x28-0x29 implementation dependent
87 ASI_LDTX_AIUP_L = 0x2A,
88 ASI_TWINX_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
89 ASI_ST_BLKINIT_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
90 ASI_STBI_AIUP_L = ASI_LDTX_AIUP_L,
91 ASI_LDTX_AIUS_L = 0x2B,
92 ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
93 ASI_ST_BLKINIT_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
94 ASI_STBI_AIUS_L = ASI_LDTX_AIUS_L,
95 ASI_LTX_L = 0x2C,
96 ASI_TWINX_LITTLE = ASI_LTX_L,
97 // 0x2D implementation dependent
98 ASI_LDTX_REAL_L = 0x2E,
99 ASI_LD_TWINX_REAL_LITTLE = ASI_LDTX_REAL_L,
100 ASI_LDTX_NL = 0x2F,
101 ASI_LD_TWINX_NUCLEUS_LITTLE = ASI_LDTX_NL,
102 // 0x20 implementation dependent
103 ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x31,
104 ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x32,
105 ASI_DMMU_CTXT_ZERO_CONFIG = 0x33,
106 // 0x34 implementation dependent
107 ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x35,
108 ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x36,
109 ASI_IMMU_CTXT_ZERO_CONFIG = 0x37,
110 // 0x38 implementation dependent
111 ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x39,
112 ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3A,
113 ASI_DMMU_CTXT_NONZERO_CONFIG = 0x3B,
114 // 0x3C implementation dependent
115 ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x3D,
116 ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3E,
117 ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F,
118 ASI_STREAM_MA = 0x40,
119 ASI_CMT_SHARED = 0x41,
120 // 0x41 implementation dependent
121 ASI_SPARC_BIST_CONTROL = 0x42,
122 ASI_INST_MASK_REG = 0x42,
123 ASI_LSU_DIAG_REG = 0x42,
124 // 0x43 implementation dependent
125 ASI_STM_CTL_REG = 0x44,
126 ASI_LSU_CONTROL_REG = 0x45,
127 ASI_DCACHE_DATA = 0x46,
128 ASI_DCACHE_TAG = 0x47,
129 ASI_INTR_DISPATCH_STATUS = 0x48,
130 ASI_INTR_RECEIVE = 0x49,
131 ASI_UPA_CONFIG_REGISTER = 0x4A,
132 ASI_SPARC_ERROR_EN_REG = 0x4B,
133 ASI_SPARC_ERROR_STATUS_REG = 0x4C,
134 ASI_SPARC_ERROR_ADDRESS_REG = 0x4D,
135 ASI_ECACHE_TAG_DATA = 0x4E,
136 ASI_HYP_SCRATCHPAD = 0x4F,
137 ASI_IMMU = 0x50,
138 ASI_IMMU_TSB_PS0_PTR_REG = 0x51,
139 ASI_IMMU_TSB_PS1_PTR_REG = 0x52,
140 // 0x53 implementation dependent
141 ASI_ITLB_DATA_IN_REG = 0x54,
142 ASI_ITLB_DATA_ACCESS_REG = 0x55,
143 ASI_ITLB_TAG_READ_REG = 0x56,
144 ASI_IMMU_DEMAP = 0x57,
145 ASI_DMMU = 0x58,
146 ASI_DMMU_TSB_PS0_PTR_REG = 0x59,
147 ASI_DMMU_TSB_PS1_PTR_REG = 0x5A,
148 ASI_DMMU_TSB_DIRECT_PTR_REG = 0x5B,
149 ASI_DTLB_DATA_IN_REG = 0x5C,
150 ASI_DTLB_DATA_ACCESS_REG = 0x5D,
151 ASI_DTLB_TAG_READ_REG = 0x5E,
152 ASI_DMMU_DEMAP = 0x5F,
153 ASI_TLB_INVALIDATE_ALL = 0x60,
154 // 0x61-0x62 implementation dependent
155 ASI_CMT_PER_STRAND = 0x63,
156 // 0x64-0x65 implementation dependent
157 ASI_ICACHE_INSTR = 0x66,
158 ASI_ICACHE_TAG = 0x67,
159 // 0x68-0x71 implementation dependent
160 ASI_SWVR_INTR_RECEIVE = 0x72,
161 ASI_SWVR_UDB_INTR_W = 0x73,
162 ASI_SWVR_UDB_INTR_R = 0x74,
163 // 0x74-0x7F reserved
164 /* Unpriveleged ASIs */
165 ASI_P = 0x80,
166 ASI_PRIMARY = ASI_P,
167 ASI_S = 0x81,
168 ASI_SECONDARY = ASI_S,
169 ASI_PNF = 0x82,
170 ASI_PRIMARY_NO_FAULT = ASI_PNF,
171 ASI_SNF = 0x83,
172 ASI_SECONDARY_NO_FAULT = ASI_SNF,
173 // 0x84-0x87 reserved
174 ASI_PL = 0x88,
175 ASI_PRIMARY_LITTLE = ASI_PL,
176 ASI_SL = 0x89,
177 ASI_SECONDARY_LITTLE = ASI_SL,
178 ASI_PNFL = 0x8A,
179 ASI_PRIMARY_NO_FAULT_LITTLE = ASI_PNFL,
180 ASI_SNFL = 0x8B,
181 ASI_SECONDARY_NO_FAULT_LITTLE = ASI_SNFL,
182 // 0x8C-0xBF reserved
183 ASI_PST8_P = 0xC0,
184 ASI_PST8_PRIMARY = ASI_PST8_P,
185 ASI_PST8_S = 0xC1,
186 ASI_PST8_SECONDARY = ASI_PST8_S,
187 ASI_PST16_P = 0xC2,
188 ASI_PST16_PRIMARY = ASI_PST16_P,
189 ASI_PST16_S = 0xC3,
190 ASI_PST16_SECONDARY = ASI_PST16_S,
191 ASI_PST32_P = 0xC4,
192 ASI_PST32_PRIMARY = ASI_PST32_P,
193 ASI_PST32_S = 0xC5,
194 ASI_PST32_SECONDARY = ASI_PST32_S,
195 // 0xC6-0xC7 implementation dependent
196 ASI_PST8_PL = 0xC8,
197 ASI_PST8_PRIMARY_LITTLE = ASI_PST8_PL,
198 ASI_PST8_SL = 0xC9,
199 ASI_PST8_SECONDARY_LITTLE = ASI_PST8_SL,
200 ASI_PST16_PL = 0xCA,
201 ASI_PST16_PRIMARY_LITTLE = ASI_PST16_PL,
202 ASI_PST16_SL = 0xCB,
203 ASI_PST16_SECONDARY_LITTLE = ASI_PST16_SL,
204 ASI_PST32_PL = 0xCC,
205 ASI_PST32_PRIMARY_LITTLE = ASI_PST32_PL,
206 ASI_PST32_SL = 0xCD,
207 ASI_PST32_SECONDARY_LITTLE = ASI_PST32_SL,
208 // 0xCE-0xCF implementation dependent
209 ASI_FL8_P = 0xD0,
210 ASI_FL8_PRIMARY = ASI_FL8_P,
211 ASI_FL8_S = 0xD1,
212 ASI_FL8_SECONDARY = ASI_FL8_S,
213 ASI_FL16_P = 0xD2,
214 ASI_FL16_PRIMARY = ASI_FL16_P,
215 ASI_FL16_S = 0xD3,
216 ASI_FL16_SECONDARY = ASI_FL16_S,
217 // 0xD4-0xD7 implementation dependent
218 ASI_FL8_PL = 0xD8,
219 ASI_FL8_PRIMARY_LITTLE = ASI_FL8_PL,
220 ASI_FL8_SL = 0xD9,
221 ASI_FL8_SECONDARY_LITTLE = ASI_FL8_SL,
222 ASI_FL16_PL = 0xDA,
223 ASI_FL16_PRIMARY_LITTLE = ASI_FL16_PL,
224 ASI_FL16_SL = 0xDB,
225 ASI_FL16_SECONDARY_LITTLE = ASI_FL16_SL,
226 // 0xDC-0xDF implementation dependent
227 // 0xE0-0xE1 reserved
228 ASI_LDTX_P = 0xE2,
229 ASI_LD_TWINX_PRIMARY = ASI_LDTX_P,
230 ASI_LDTX_S = 0xE3,
231 ASI_LD_TWINX_SECONDARY = ASI_LDTX_S,
232 // 0xE4-0xE9 implementation dependent
233 ASI_LDTX_PL = 0xEA,
234 ASI_LD_TWINX_PRIMARY_LITTLE = ASI_LDTX_PL,
235 ASI_LDTX_SL = 0xEB,
236 ASI_LD_TWINX_SECONDARY_LITTLE = ASI_LDTX_SL,
237 // 0xEC-0xEF implementation dependent
238 ASI_BLK_P = 0xF0,
239 ASI_BLOCK_PRIMARY = ASI_BLK_P,
240 ASI_BLK_S = 0xF1,
241 ASI_BLOCK_SECONDARY = ASI_BLK_S,
242 // 0xF2-0xF7 implementation dependent
243 ASI_BLK_PL = 0xF8,
244 ASI_BLOCK_PRIMARY_LITTLE = ASI_BLK_PL,
245 ASI_BLK_SL = 0xF9,
246 ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL,
247 // 0xFA-0xFF implementation dependent
248 MAX_ASI = 0xFF
274};
275
249};
250
251// Functions that classify an asi
252bool asiIsBlock(ASI);
253bool asiIsPrimary(ASI);
254bool asiIsSecondary(ASI);
255bool asiIsNucleus(ASI);
256bool asiIsAsIfUser(ASI);
257bool asiIsIO(ASI);
258bool asiIsReal(ASI);
259bool asiIsLittle(ASI);
260bool asiIsTwin(ASI);
261bool asiIsPartialStore(ASI);
262bool asiIsFloatingLoad(ASI);
263bool asiIsNoFault(ASI);
264bool asiIsScratchPad(ASI);
265bool asiIsCmt(ASI);
266bool asiIsQueue(ASI);
267bool asiIsDtlb(ASI);
268bool asiIsMmu(ASI);
269bool asiIsUnPriv(ASI);
270bool asiIsPriv(ASI);
271bool asiIsHPriv(ASI);
272bool asiIsReg(ASI);
273bool asiIsInterrupt(ASI);
274bool asiIsSparcError(ASI);
275};
276
276#endif // __ARCH_SPARC_ASI_HH__
277#endif // __ARCH_SPARC_ASI_HH__