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> * Ali Saidi
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< ASI_AIUPL = 0x18,
< ASI_AS_IF_USER_PRIMARY_LITTLE = ASI_AIUPL,
< ASI_AIUSL = 0x19,
< ASI_AS_IF_USER_SECONDARY_LITTLE = ASI_AIUSL,
---
> ASI_AIUP_L = 0x18,
> ASI_AS_IF_USER_PRIMARY_LITTLE = ASI_AIUP_L,
> ASI_AIUS_L = 0x19,
> ASI_AS_IF_USER_SECONDARY_LITTLE = ASI_AIUS_L,
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< ASI_BLK_AIUPL = 0x1E,
< ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = ASI_BLK_AIUPL,
< ASI_BLK_AIUSL = 0x1F,
< ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = ASI_BLK_AIUSL,
---
> ASI_BLK_AIUP_L = 0x1E,
> ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = ASI_BLK_AIUP_L,
> ASI_BLK_AIUS_L = 0x1F,
> ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = ASI_BLK_AIUS_L,
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< ASI_MMU_CONTEXTID = 0x21,
---
> ASI_MMU = 0x21,
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< //0x24 implementation dependent
---
> ASI_QUAD_LDD = 0x24,
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< ASI_LDTX_REAL = 0x26,
< ASI_LD_TWINX_REAL = ASI_LDTX_REAL,
---
> ASI_QUAD_LDD_REAL = 0x26,
> ASI_LDTX_REAL = ASI_QUAD_LDD_REAL,
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> ASI_ST_BLKINIT_NUCLEUS = ASI_LDTX_N,
> ASI_STBI_N = ASI_LDTX_N,
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< ASI_LDTX_AIUPL = 0x2A,
< ASI_LD_TWINX_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUPL,
< ASI_LDTX_AIUSL = 0x2B,
< ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUSL,
< //0x2C-0x2D implementation dependent
---
> ASI_LDTX_AIUP_L = 0x2A,
> ASI_TWINX_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
> ASI_ST_BLKINIT_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
> ASI_STBI_AIUP_L = ASI_LDTX_AIUP_L,
> ASI_LDTX_AIUS_L = 0x2B,
> ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
> ASI_ST_BLKINIT_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
> ASI_STBI_AIUS_L = ASI_LDTX_AIUS_L,
> ASI_LTX_L = 0x2C,
> ASI_TWINX_LITTLE = ASI_LTX_L,
> //0x2D implementation dependent
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< //0x30-0x40 implementation dependent
< ASI_CMT_SHARED = 0x41,
< //0x42-0x4F implementation dependent
---
> //0x20 implementation dependent
> ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x31,
> ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x32,
> ASI_DMMU_CTXT_ZERO_CONFIG = 0x33,
> //0x34 implementation dependent
> ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x35,
> ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x36,
> ASI_IMMU_CTXT_ZERO_CONFIG = 0x37,
> //0x38 implementation dependent
> ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x39,
> ASI_DMMU_CTXT_NONZERO_USB_BASE_PS1 = 0x3A,
> ASI_DMMU_CTXT_NONZERO_CONFIG = 0x3B,
> //0x3C implementation dependent
> ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x3D,
> ASI_IMMU_CTXT_NONZERO_USB_BASE_PS1 = 0x3E,
> ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F,
> ASI_STREAM_MA = 0x40,
> //0x41 implementation dependent
> ASI_SPARC_BIST_CONTROL = 0x42,
> ASI_INST_MASK_REG = 0x42,
> ASI_LSU_DIAG_REG = 0x42,
> //0x43 implementation dependent
> ASI_STM_CTL_REG = 0x44,
> ASI_LSU_CONTROL_REG = 0x45,
> ASI_DCACHE_DATA = 0x46,
> ASI_DCACHE_TAG = 0x47,
> ASI_INTR_DISPATCH_STATUS = 0x48,
> ASI_INTR_RECEIVE = 0x49,
> ASI_UPA_CONFIG_REGISTER = 0x4A,
> ASI_SPARC_ERROR_EN_REG = 0x4B,
> ASI_SPARC_ERROR_STATUS_REG = 0x4C,
> ASI_SPARC_ERROR_ADDRESS_REG = 0x4D,
> ASI_ECACHE_TAG_DATA = 0x4E,
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< ASI_MMU_REAL = 0x52,
---
> ASI_IMMU_TSB_PS0_PTR_REG = 0x51,
> ASI_IMMU_TSB_PS1_PTR_REG = 0x52,
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< ASI_MMU = 0x54,
---
> ASI_ITLB_DATA_IN_REG = 0x54,
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< ASI_UMMU = 0x58,
< //0x59-0x5B reserved
---
> ASI_DMMU_TSB_PS0_PTR_REG = 0x59,
> ASI_DMMU_TSB_PS1_PTR_REG = 0x5A,
> ASI_DMMU_TSB_DIRECT_PTR_REG = 0x5B,
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< //0x60-62 implementation dependent
---
> ASI_TLB_INVALIDATE_ALL = 0x60,
> //0x61-0x62 implementation dependent
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< //0x64-0x67 implementation dependent
< //0x68-0x7F reserved
<
---
> //0x64-0x65 implementation dependent
> ASI_ICACHE_INSTR = 0x66,
> ASI_ICACHE_TAG = 0x67,
> //0x68-0x71 implementation dependent
> ASI_SWVR_INTR_RECEIVE = 0x72,
> ASI_SWVR_UDB_INTR_W = 0x73,
> ASI_SWVR_UDB_INTR_R = 0x74,
> //0x74-0x7F reserved
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> ASI_IMPLICIT = 0xFF,
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> bool AsiIsUnPriv(ASI);
> bool AsiIsPriv(ASI);
> bool AsiIsHPriv(ASI);
> bool AsiIsReg(ASI);