1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
|
| 29 * Ali Saidi
|
29 */
30
31#ifndef __ARCH_SPARC_ASI_HH__
32#define __ARCH_SPARC_ASI_HH__
33
34namespace SparcISA
35{
36 enum ASI {
37 /* Priveleged ASIs */
38 //0x00-0x03 implementation dependent
39 ASI_NUCLEUS = 0x4,
40 ASI_N = 0x4,
41 //0x05-0x0B implementation dependent
42 ASI_NL = 0xC,
43 ASI_NUCLEUS_LITTLE = ASI_NL,
44 //0x0D-0x0F implementation dependent
45 ASI_AIUP = 0x10,
46 ASI_AS_IF_USER_PRIMARY = ASI_AIUP,
47 ASI_AIUS = 0x11,
48 ASI_AS_IF_USER_SECONDARY = ASI_AIUS,
49 //0x12-0x13 implementation dependent
50 ASI_REAL = 0x14,
51 ASI_REAL_IO = 0x15,
52 ASI_BLK_AIUP = 0x16,
53 ASI_BLOCK_AS_IF_USER_PRIMARY = ASI_BLK_AIUP,
54 ASI_BLK_AIUS = 0x17,
55 ASI_BLOCK_AS_IF_USER_SECONDARY = ASI_BLK_AIUS,
| 30 */
31
32#ifndef __ARCH_SPARC_ASI_HH__
33#define __ARCH_SPARC_ASI_HH__
34
35namespace SparcISA
36{
37 enum ASI {
38 /* Priveleged ASIs */
39 //0x00-0x03 implementation dependent
40 ASI_NUCLEUS = 0x4,
41 ASI_N = 0x4,
42 //0x05-0x0B implementation dependent
43 ASI_NL = 0xC,
44 ASI_NUCLEUS_LITTLE = ASI_NL,
45 //0x0D-0x0F implementation dependent
46 ASI_AIUP = 0x10,
47 ASI_AS_IF_USER_PRIMARY = ASI_AIUP,
48 ASI_AIUS = 0x11,
49 ASI_AS_IF_USER_SECONDARY = ASI_AIUS,
50 //0x12-0x13 implementation dependent
51 ASI_REAL = 0x14,
52 ASI_REAL_IO = 0x15,
53 ASI_BLK_AIUP = 0x16,
54 ASI_BLOCK_AS_IF_USER_PRIMARY = ASI_BLK_AIUP,
55 ASI_BLK_AIUS = 0x17,
56 ASI_BLOCK_AS_IF_USER_SECONDARY = ASI_BLK_AIUS,
|
56 ASI_AIUPL = 0x18,
57 ASI_AS_IF_USER_PRIMARY_LITTLE = ASI_AIUPL,
58 ASI_AIUSL = 0x19,
59 ASI_AS_IF_USER_SECONDARY_LITTLE = ASI_AIUSL,
| 57 ASI_AIUP_L = 0x18,
58 ASI_AS_IF_USER_PRIMARY_LITTLE = ASI_AIUP_L,
59 ASI_AIUS_L = 0x19,
60 ASI_AS_IF_USER_SECONDARY_LITTLE = ASI_AIUS_L,
|
60 //0x1A-0x1B implementation dependent
61 ASI_REAL_L = 0x1C,
62 ASI_REAL_LITTLE = ASI_REAL_L,
63 ASI_REAL_IO_L = 0x1D,
64 ASI_REAL_IO_LITTLE = ASI_REAL_IO_L,
| 61 //0x1A-0x1B implementation dependent
62 ASI_REAL_L = 0x1C,
63 ASI_REAL_LITTLE = ASI_REAL_L,
64 ASI_REAL_IO_L = 0x1D,
65 ASI_REAL_IO_LITTLE = ASI_REAL_IO_L,
|
65 ASI_BLK_AIUPL = 0x1E,
66 ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = ASI_BLK_AIUPL,
67 ASI_BLK_AIUSL = 0x1F,
68 ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = ASI_BLK_AIUSL,
| 66 ASI_BLK_AIUP_L = 0x1E,
67 ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = ASI_BLK_AIUP_L,
68 ASI_BLK_AIUS_L = 0x1F,
69 ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = ASI_BLK_AIUS_L,
|
69 ASI_SCRATCHPAD = 0x20,
| 70 ASI_SCRATCHPAD = 0x20,
|
70 ASI_MMU_CONTEXTID = 0x21,
| 71 ASI_MMU = 0x21,
|
71 ASI_LDTX_AIUP = 0x22,
72 ASI_LD_TWINX_AS_IF_USER_PRIMARY = ASI_LDTX_AIUP,
73 ASI_LDTX_AIUS = 0x23,
74 ASI_LD_TWINX_AS_IF_USER_SECONDARY = ASI_LDTX_AIUS,
| 72 ASI_LDTX_AIUP = 0x22,
73 ASI_LD_TWINX_AS_IF_USER_PRIMARY = ASI_LDTX_AIUP,
74 ASI_LDTX_AIUS = 0x23,
75 ASI_LD_TWINX_AS_IF_USER_SECONDARY = ASI_LDTX_AIUS,
|
75 //0x24 implementation dependent
| 76 ASI_QUAD_LDD = 0x24,
|
76 ASI_QUEUE = 0x25,
| 77 ASI_QUEUE = 0x25,
|
77 ASI_LDTX_REAL = 0x26,
78 ASI_LD_TWINX_REAL = ASI_LDTX_REAL,
| 78 ASI_QUAD_LDD_REAL = 0x26,
79 ASI_LDTX_REAL = ASI_QUAD_LDD_REAL,
|
79 ASI_LDTX_N = 0x27,
80 ASI_LD_TWINX_NUCLEUS = ASI_LDTX_N,
| 80 ASI_LDTX_N = 0x27,
81 ASI_LD_TWINX_NUCLEUS = ASI_LDTX_N,
|
| 82 ASI_ST_BLKINIT_NUCLEUS = ASI_LDTX_N,
83 ASI_STBI_N = ASI_LDTX_N,
|
81 //0x28-0x29 implementation dependent
| 84 //0x28-0x29 implementation dependent
|
82 ASI_LDTX_AIUPL = 0x2A,
83 ASI_LD_TWINX_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUPL,
84 ASI_LDTX_AIUSL = 0x2B,
85 ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUSL,
86 //0x2C-0x2D implementation dependent
| 85 ASI_LDTX_AIUP_L = 0x2A,
86 ASI_TWINX_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
87 ASI_ST_BLKINIT_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
88 ASI_STBI_AIUP_L = ASI_LDTX_AIUP_L,
89 ASI_LDTX_AIUS_L = 0x2B,
90 ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
91 ASI_ST_BLKINIT_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
92 ASI_STBI_AIUS_L = ASI_LDTX_AIUS_L,
93 ASI_LTX_L = 0x2C,
94 ASI_TWINX_LITTLE = ASI_LTX_L,
95 //0x2D implementation dependent
|
87 ASI_LDTX_REAL_L = 0x2E,
88 ASI_LD_TWINX_REAL_LITTLE = ASI_LDTX_REAL_L,
89 ASI_LDTX_NL = 0x2F,
90 ASI_LD_TWINX_NUCLEUS_LITTLE = ASI_LDTX_NL,
| 96 ASI_LDTX_REAL_L = 0x2E,
97 ASI_LD_TWINX_REAL_LITTLE = ASI_LDTX_REAL_L,
98 ASI_LDTX_NL = 0x2F,
99 ASI_LD_TWINX_NUCLEUS_LITTLE = ASI_LDTX_NL,
|
91 //0x30-0x40 implementation dependent
92 ASI_CMT_SHARED = 0x41,
93 //0x42-0x4F implementation dependent
| 100 //0x20 implementation dependent
101 ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x31,
102 ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x32,
103 ASI_DMMU_CTXT_ZERO_CONFIG = 0x33,
104 //0x34 implementation dependent
105 ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x35,
106 ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x36,
107 ASI_IMMU_CTXT_ZERO_CONFIG = 0x37,
108 //0x38 implementation dependent
109 ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x39,
110 ASI_DMMU_CTXT_NONZERO_USB_BASE_PS1 = 0x3A,
111 ASI_DMMU_CTXT_NONZERO_CONFIG = 0x3B,
112 //0x3C implementation dependent
113 ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x3D,
114 ASI_IMMU_CTXT_NONZERO_USB_BASE_PS1 = 0x3E,
115 ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F,
116 ASI_STREAM_MA = 0x40,
117 //0x41 implementation dependent
118 ASI_SPARC_BIST_CONTROL = 0x42,
119 ASI_INST_MASK_REG = 0x42,
120 ASI_LSU_DIAG_REG = 0x42,
121 //0x43 implementation dependent
122 ASI_STM_CTL_REG = 0x44,
123 ASI_LSU_CONTROL_REG = 0x45,
124 ASI_DCACHE_DATA = 0x46,
125 ASI_DCACHE_TAG = 0x47,
126 ASI_INTR_DISPATCH_STATUS = 0x48,
127 ASI_INTR_RECEIVE = 0x49,
128 ASI_UPA_CONFIG_REGISTER = 0x4A,
129 ASI_SPARC_ERROR_EN_REG = 0x4B,
130 ASI_SPARC_ERROR_STATUS_REG = 0x4C,
131 ASI_SPARC_ERROR_ADDRESS_REG = 0x4D,
132 ASI_ECACHE_TAG_DATA = 0x4E,
|
94 ASI_HYP_SCRATCHPAD = 0x4F,
95 ASI_IMMU = 0x50,
| 133 ASI_HYP_SCRATCHPAD = 0x4F,
134 ASI_IMMU = 0x50,
|
96 ASI_MMU_REAL = 0x52,
| 135 ASI_IMMU_TSB_PS0_PTR_REG = 0x51,
136 ASI_IMMU_TSB_PS1_PTR_REG = 0x52,
|
97 //0x53 implementation dependent
| 137 //0x53 implementation dependent
|
98 ASI_MMU = 0x54,
| 138 ASI_ITLB_DATA_IN_REG = 0x54,
|
99 ASI_ITLB_DATA_ACCESS_REG = 0x55,
100 ASI_ITLB_TAG_READ_REG = 0x56,
101 ASI_IMMU_DEMAP = 0x57,
102 ASI_DMMU = 0x58,
| 139 ASI_ITLB_DATA_ACCESS_REG = 0x55,
140 ASI_ITLB_TAG_READ_REG = 0x56,
141 ASI_IMMU_DEMAP = 0x57,
142 ASI_DMMU = 0x58,
|
103 ASI_UMMU = 0x58,
104 //0x59-0x5B reserved
| 143 ASI_DMMU_TSB_PS0_PTR_REG = 0x59,
144 ASI_DMMU_TSB_PS1_PTR_REG = 0x5A,
145 ASI_DMMU_TSB_DIRECT_PTR_REG = 0x5B,
|
105 ASI_DTLB_DATA_IN_REG = 0x5C,
106 ASI_DTLB_DATA_ACCESS_REG = 0x5D,
107 ASI_DTLB_TAG_READ_REG = 0x5E,
108 ASI_DMMU_DEMAP = 0x5F,
| 146 ASI_DTLB_DATA_IN_REG = 0x5C,
147 ASI_DTLB_DATA_ACCESS_REG = 0x5D,
148 ASI_DTLB_TAG_READ_REG = 0x5E,
149 ASI_DMMU_DEMAP = 0x5F,
|
109 //0x60-62 implementation dependent
| 150 ASI_TLB_INVALIDATE_ALL = 0x60,
151 //0x61-0x62 implementation dependent
|
110 ASI_CMT_PER_STRAND = 0x63,
| 152 ASI_CMT_PER_STRAND = 0x63,
|
111 //0x64-0x67 implementation dependent
112 //0x68-0x7F reserved
113
| 153 //0x64-0x65 implementation dependent
154 ASI_ICACHE_INSTR = 0x66,
155 ASI_ICACHE_TAG = 0x67,
156 //0x68-0x71 implementation dependent
157 ASI_SWVR_INTR_RECEIVE = 0x72,
158 ASI_SWVR_UDB_INTR_W = 0x73,
159 ASI_SWVR_UDB_INTR_R = 0x74,
160 //0x74-0x7F reserved
|
114 /* Unpriveleged ASIs */
115 ASI_P = 0x80,
116 ASI_PRIMARY = ASI_P,
117 ASI_S = 0x81,
118 ASI_SECONDARY = ASI_S,
119 ASI_PNF = 0x82,
120 ASI_PRIMARY_NO_FAULT = ASI_PNF,
121 ASI_SNF = 0x83,
122 ASI_SECONDARY_NO_FAULT = ASI_SNF,
123 //0x84-0x87 reserved
124 ASI_PL = 0x88,
125 ASI_PRIMARY_LITTLE = ASI_PL,
126 ASI_SL = 0x89,
127 ASI_SECONDARY_LITTLE = ASI_SL,
128 ASI_PNFL = 0x8A,
129 ASI_PRIMARY_NO_FAULT_LITTLE = ASI_PNFL,
130 ASI_SNFL = 0x8B,
131 ASI_SECONDARY_NO_FAULT_LITTLE = ASI_SNFL,
132 //0x8C-0xBF reserved
133 ASI_PST8_P = 0xC0,
134 ASI_PST8_PRIMARY = ASI_PST8_P,
135 ASI_PST8_S = 0xC1,
136 ASI_PST8_SECONDARY = ASI_PST8_S,
137 ASI_PST16_P = 0xC2,
138 ASI_PST16_PRIMARY = ASI_PST16_P,
139 ASI_PST16_S = 0xC3,
140 ASI_PST16_SECONDARY = ASI_PST16_S,
141 ASI_PST32_P = 0xC4,
142 ASI_PST32_PRIMARY = ASI_PST32_P,
143 ASI_PST32_S = 0xC5,
144 ASI_PST32_SECONDARY = ASI_PST32_S,
145 //0xC6-0xC7 implementation dependent
146 ASI_PST8_PL = 0xC8,
147 ASI_PST8_PRIMARY_LITTLE = ASI_PST8_PL,
148 ASI_PST8_SL = 0xC9,
149 ASI_PST8_SECONDARY_LITTLE = ASI_PST8_SL,
150 ASI_PST16_PL = 0xCA,
151 ASI_PST16_PRIMARY_LITTLE = ASI_PST16_PL,
152 ASI_PST16_SL = 0xCB,
153 ASI_PST16_SECONDARY_LITTLE = ASI_PST16_SL,
154 ASI_PST32_PL = 0xCC,
155 ASI_PST32_PRIMARY_LITTLE = ASI_PST32_PL,
156 ASI_PST32_SL = 0xCD,
157 ASI_PST32_SECONDARY_LITTLE = ASI_PST32_SL,
158 //0xCE-0xCF implementation dependent
159 ASI_FL8_P = 0xD0,
160 ASI_FL8_PRIMARY = ASI_FL8_P,
161 ASI_FL8_S = 0xD1,
162 ASI_FL8_SECONDARY = ASI_FL8_S,
163 ASI_FL16_P = 0xD2,
164 ASI_FL16_PRIMARY = ASI_FL16_P,
165 ASI_FL16_S = 0xD3,
166 ASI_FL16_SECONDARY = ASI_FL16_S,
167 //0xD4-0xD7 implementation dependent
168 ASI_FL8_PL = 0xD8,
169 ASI_FL8_PRIMARY_LITTLE = ASI_FL8_PL,
170 ASI_FL8_SL = 0xD9,
171 ASI_FL8_SECONDARY_LITTLE = ASI_FL8_SL,
172 ASI_FL16_PL = 0xDA,
173 ASI_FL16_PRIMARY_LITTLE = ASI_FL16_PL,
174 ASI_FL16_SL = 0xDB,
175 ASI_FL16_SECONDARY_LITTLE = ASI_FL16_SL,
176 //0xDC-0xDF implementation dependent
177 //0xE0-0xE1 reserved
178 ASI_LDTX_P = 0xE2,
179 ASI_LD_TWINX_PRIMARY = ASI_LDTX_P,
180 ASI_LDTX_S = 0xE3,
181 ASI_LD_TWINX_SECONDARY = ASI_LDTX_S,
182 //0xE4-0xE9 implementation dependent
183 ASI_LDTX_PL = 0xEA,
184 ASI_LD_TWINX_PRIMARY_LITTLE = ASI_LDTX_PL,
185 ASI_LDTX_SL = 0xEB,
186 ASI_LD_TWINX_SECONDARY_LITTLE = ASI_LDTX_SL,
187 //0xEC-0xEF implementation dependent
188 ASI_BLK_P = 0xF0,
189 ASI_BLOCK_PRIMARY = ASI_BLK_P,
190 ASI_BLK_S = 0xF1,
191 ASI_BLOCK_SECONDARY = ASI_BLK_S,
192 //0xF2-0xF7 implementation dependent
193 ASI_BLK_PL = 0xF8,
194 ASI_BLOCK_PRIMARY_LITTLE = ASI_BLK_PL,
195 ASI_BLK_SL = 0xF9,
196 ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL,
197 //0xFA-0xFF implementation dependent
| 161 /* Unpriveleged ASIs */
162 ASI_P = 0x80,
163 ASI_PRIMARY = ASI_P,
164 ASI_S = 0x81,
165 ASI_SECONDARY = ASI_S,
166 ASI_PNF = 0x82,
167 ASI_PRIMARY_NO_FAULT = ASI_PNF,
168 ASI_SNF = 0x83,
169 ASI_SECONDARY_NO_FAULT = ASI_SNF,
170 //0x84-0x87 reserved
171 ASI_PL = 0x88,
172 ASI_PRIMARY_LITTLE = ASI_PL,
173 ASI_SL = 0x89,
174 ASI_SECONDARY_LITTLE = ASI_SL,
175 ASI_PNFL = 0x8A,
176 ASI_PRIMARY_NO_FAULT_LITTLE = ASI_PNFL,
177 ASI_SNFL = 0x8B,
178 ASI_SECONDARY_NO_FAULT_LITTLE = ASI_SNFL,
179 //0x8C-0xBF reserved
180 ASI_PST8_P = 0xC0,
181 ASI_PST8_PRIMARY = ASI_PST8_P,
182 ASI_PST8_S = 0xC1,
183 ASI_PST8_SECONDARY = ASI_PST8_S,
184 ASI_PST16_P = 0xC2,
185 ASI_PST16_PRIMARY = ASI_PST16_P,
186 ASI_PST16_S = 0xC3,
187 ASI_PST16_SECONDARY = ASI_PST16_S,
188 ASI_PST32_P = 0xC4,
189 ASI_PST32_PRIMARY = ASI_PST32_P,
190 ASI_PST32_S = 0xC5,
191 ASI_PST32_SECONDARY = ASI_PST32_S,
192 //0xC6-0xC7 implementation dependent
193 ASI_PST8_PL = 0xC8,
194 ASI_PST8_PRIMARY_LITTLE = ASI_PST8_PL,
195 ASI_PST8_SL = 0xC9,
196 ASI_PST8_SECONDARY_LITTLE = ASI_PST8_SL,
197 ASI_PST16_PL = 0xCA,
198 ASI_PST16_PRIMARY_LITTLE = ASI_PST16_PL,
199 ASI_PST16_SL = 0xCB,
200 ASI_PST16_SECONDARY_LITTLE = ASI_PST16_SL,
201 ASI_PST32_PL = 0xCC,
202 ASI_PST32_PRIMARY_LITTLE = ASI_PST32_PL,
203 ASI_PST32_SL = 0xCD,
204 ASI_PST32_SECONDARY_LITTLE = ASI_PST32_SL,
205 //0xCE-0xCF implementation dependent
206 ASI_FL8_P = 0xD0,
207 ASI_FL8_PRIMARY = ASI_FL8_P,
208 ASI_FL8_S = 0xD1,
209 ASI_FL8_SECONDARY = ASI_FL8_S,
210 ASI_FL16_P = 0xD2,
211 ASI_FL16_PRIMARY = ASI_FL16_P,
212 ASI_FL16_S = 0xD3,
213 ASI_FL16_SECONDARY = ASI_FL16_S,
214 //0xD4-0xD7 implementation dependent
215 ASI_FL8_PL = 0xD8,
216 ASI_FL8_PRIMARY_LITTLE = ASI_FL8_PL,
217 ASI_FL8_SL = 0xD9,
218 ASI_FL8_SECONDARY_LITTLE = ASI_FL8_SL,
219 ASI_FL16_PL = 0xDA,
220 ASI_FL16_PRIMARY_LITTLE = ASI_FL16_PL,
221 ASI_FL16_SL = 0xDB,
222 ASI_FL16_SECONDARY_LITTLE = ASI_FL16_SL,
223 //0xDC-0xDF implementation dependent
224 //0xE0-0xE1 reserved
225 ASI_LDTX_P = 0xE2,
226 ASI_LD_TWINX_PRIMARY = ASI_LDTX_P,
227 ASI_LDTX_S = 0xE3,
228 ASI_LD_TWINX_SECONDARY = ASI_LDTX_S,
229 //0xE4-0xE9 implementation dependent
230 ASI_LDTX_PL = 0xEA,
231 ASI_LD_TWINX_PRIMARY_LITTLE = ASI_LDTX_PL,
232 ASI_LDTX_SL = 0xEB,
233 ASI_LD_TWINX_SECONDARY_LITTLE = ASI_LDTX_SL,
234 //0xEC-0xEF implementation dependent
235 ASI_BLK_P = 0xF0,
236 ASI_BLOCK_PRIMARY = ASI_BLK_P,
237 ASI_BLK_S = 0xF1,
238 ASI_BLOCK_SECONDARY = ASI_BLK_S,
239 //0xF2-0xF7 implementation dependent
240 ASI_BLK_PL = 0xF8,
241 ASI_BLOCK_PRIMARY_LITTLE = ASI_BLK_PL,
242 ASI_BLK_SL = 0xF9,
243 ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL,
244 //0xFA-0xFF implementation dependent
|
| 245 ASI_IMPLICIT = 0xFF,
|
198 MAX_ASI = 0xFF
199 };
200
201 //Functions that classify an asi
202 bool AsiIsBlock(ASI);
203 bool AsiIsPrimary(ASI);
204 bool AsiIsSecondary(ASI);
205 bool AsiIsNucleus(ASI);
206 bool AsiIsAsIfUser(ASI);
207 bool AsiIsIO(ASI);
208 bool AsiIsReal(ASI);
209 bool AsiIsLittle(ASI);
210 bool AsiIsTwin(ASI);
211 bool AsiIsPartialStore(ASI);
212 bool AsiIsFloatingLoad(ASI);
213 bool AsiIsNoFault(ASI);
214 bool AsiIsScratchPad(ASI);
215 bool AsiIsCmt(ASI);
216 bool AsiIsQueue(ASI);
217 bool AsiIsDtlb(ASI);
218 bool AsiIsMmu(ASI);
| 246 MAX_ASI = 0xFF
247 };
248
249 //Functions that classify an asi
250 bool AsiIsBlock(ASI);
251 bool AsiIsPrimary(ASI);
252 bool AsiIsSecondary(ASI);
253 bool AsiIsNucleus(ASI);
254 bool AsiIsAsIfUser(ASI);
255 bool AsiIsIO(ASI);
256 bool AsiIsReal(ASI);
257 bool AsiIsLittle(ASI);
258 bool AsiIsTwin(ASI);
259 bool AsiIsPartialStore(ASI);
260 bool AsiIsFloatingLoad(ASI);
261 bool AsiIsNoFault(ASI);
262 bool AsiIsScratchPad(ASI);
263 bool AsiIsCmt(ASI);
264 bool AsiIsQueue(ASI);
265 bool AsiIsDtlb(ASI);
266 bool AsiIsMmu(ASI);
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| 267 bool AsiIsUnPriv(ASI);
268 bool AsiIsPriv(ASI);
269 bool AsiIsHPriv(ASI);
270 bool AsiIsReg(ASI);
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219
220};
221
222#endif // __ARCH_SPARC_ASI_HH__
| 271
272};
273
274#endif // __ARCH_SPARC_ASI_HH__
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