1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_ASI_HH__
32#define __ARCH_SPARC_ASI_HH__
33
34namespace SparcISA
35{
36 enum ASI {

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48 ASI_AS_IF_USER_SECONDARY = ASI_AIUS,
49 //0x12-0x13 implementation dependent
50 ASI_REAL = 0x14,
51 ASI_REAL_IO = 0x15,
52 ASI_BLK_AIUP = 0x16,
53 ASI_BLOCK_AS_IF_USER_PRIMARY = ASI_BLK_AIUP,
54 ASI_BLK_AIUS = 0x17,
55 ASI_BLOCK_AS_IF_USER_SECONDARY = ASI_BLK_AIUS,
56 ASI_AIUPL = 0x18,
57 ASI_AS_IF_USER_PRIMARY_LITTLE = ASI_AIUPL,
58 ASI_AIUSL = 0x19,
59 ASI_AS_IF_USER_SECONDARY_LITTLE = ASI_AIUSL,
60 //0x1A-0x1B implementation dependent
61 ASI_REAL_L = 0x1C,
62 ASI_REAL_LITTLE = ASI_REAL_L,
63 ASI_REAL_IO_L = 0x1D,
64 ASI_REAL_IO_LITTLE = ASI_REAL_IO_L,
65 ASI_BLK_AIUPL = 0x1E,
66 ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = ASI_BLK_AIUPL,
67 ASI_BLK_AIUSL = 0x1F,
68 ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = ASI_BLK_AIUSL,
69 ASI_SCRATCHPAD = 0x20,
70 ASI_MMU_CONTEXTID = 0x21,
71 ASI_LDTX_AIUP = 0x22,
72 ASI_LD_TWINX_AS_IF_USER_PRIMARY = ASI_LDTX_AIUP,
73 ASI_LDTX_AIUS = 0x23,
74 ASI_LD_TWINX_AS_IF_USER_SECONDARY = ASI_LDTX_AIUS,
75 //0x24 implementation dependent
76 ASI_QUEUE = 0x25,
77 ASI_LDTX_REAL = 0x26,
78 ASI_LD_TWINX_REAL = ASI_LDTX_REAL,
79 ASI_LDTX_N = 0x27,
80 ASI_LD_TWINX_NUCLEUS = ASI_LDTX_N,
81 //0x28-0x29 implementation dependent
82 ASI_LDTX_AIUPL = 0x2A,
83 ASI_LD_TWINX_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUPL,
84 ASI_LDTX_AIUSL = 0x2B,
85 ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUSL,
86 //0x2C-0x2D implementation dependent
87 ASI_LDTX_REAL_L = 0x2E,
88 ASI_LD_TWINX_REAL_LITTLE = ASI_LDTX_REAL_L,
89 ASI_LDTX_NL = 0x2F,
90 ASI_LD_TWINX_NUCLEUS_LITTLE = ASI_LDTX_NL,
91 //0x30-0x40 implementation dependent
92 ASI_CMT_SHARED = 0x41,
93 //0x42-0x4F implementation dependent
94 ASI_HYP_SCRATCHPAD = 0x4F,
95 ASI_IMMU = 0x50,
96 ASI_MMU_REAL = 0x52,
97 //0x53 implementation dependent
98 ASI_MMU = 0x54,
99 ASI_ITLB_DATA_ACCESS_REG = 0x55,
100 ASI_ITLB_TAG_READ_REG = 0x56,
101 ASI_IMMU_DEMAP = 0x57,
102 ASI_DMMU = 0x58,
103 ASI_UMMU = 0x58,
104 //0x59-0x5B reserved
105 ASI_DTLB_DATA_IN_REG = 0x5C,
106 ASI_DTLB_DATA_ACCESS_REG = 0x5D,
107 ASI_DTLB_TAG_READ_REG = 0x5E,
108 ASI_DMMU_DEMAP = 0x5F,
109 //0x60-62 implementation dependent
110 ASI_CMT_PER_STRAND = 0x63,
111 //0x64-0x67 implementation dependent
112 //0x68-0x7F reserved
113
114 /* Unpriveleged ASIs */
115 ASI_P = 0x80,
116 ASI_PRIMARY = ASI_P,
117 ASI_S = 0x81,
118 ASI_SECONDARY = ASI_S,
119 ASI_PNF = 0x82,
120 ASI_PRIMARY_NO_FAULT = ASI_PNF,
121 ASI_SNF = 0x83,

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190 ASI_BLK_S = 0xF1,
191 ASI_BLOCK_SECONDARY = ASI_BLK_S,
192 //0xF2-0xF7 implementation dependent
193 ASI_BLK_PL = 0xF8,
194 ASI_BLOCK_PRIMARY_LITTLE = ASI_BLK_PL,
195 ASI_BLK_SL = 0xF9,
196 ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL,
197 //0xFA-0xFF implementation dependent
198 MAX_ASI = 0xFF
199 };
200
201 //Functions that classify an asi
202 bool AsiIsBlock(ASI);
203 bool AsiIsPrimary(ASI);
204 bool AsiIsSecondary(ASI);
205 bool AsiIsNucleus(ASI);

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211 bool AsiIsPartialStore(ASI);
212 bool AsiIsFloatingLoad(ASI);
213 bool AsiIsNoFault(ASI);
214 bool AsiIsScratchPad(ASI);
215 bool AsiIsCmt(ASI);
216 bool AsiIsQueue(ASI);
217 bool AsiIsDtlb(ASI);
218 bool AsiIsMmu(ASI);
219
220};
221
222#endif // __ARCH_SPARC_ASI_HH__