1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
--- 12 unchanged lines hidden (view full) ---
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32#ifndef __ARCH_SPARC_ASI_HH__
33#define __ARCH_SPARC_ASI_HH__
34
35namespace SparcISA
36{
37 enum ASI {
--- 11 unchanged lines hidden (view full) ---
49 ASI_AS_IF_USER_SECONDARY = ASI_AIUS,
50 //0x12-0x13 implementation dependent
51 ASI_REAL = 0x14,
52 ASI_REAL_IO = 0x15,
53 ASI_BLK_AIUP = 0x16,
54 ASI_BLOCK_AS_IF_USER_PRIMARY = ASI_BLK_AIUP,
55 ASI_BLK_AIUS = 0x17,
56 ASI_BLOCK_AS_IF_USER_SECONDARY = ASI_BLK_AIUS,
57 ASI_AIUP_L = 0x18,
58 ASI_AS_IF_USER_PRIMARY_LITTLE = ASI_AIUP_L,
59 ASI_AIUS_L = 0x19,
60 ASI_AS_IF_USER_SECONDARY_LITTLE = ASI_AIUS_L,
61 //0x1A-0x1B implementation dependent
62 ASI_REAL_L = 0x1C,
63 ASI_REAL_LITTLE = ASI_REAL_L,
64 ASI_REAL_IO_L = 0x1D,
65 ASI_REAL_IO_LITTLE = ASI_REAL_IO_L,
66 ASI_BLK_AIUP_L = 0x1E,
67 ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = ASI_BLK_AIUP_L,
68 ASI_BLK_AIUS_L = 0x1F,
69 ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = ASI_BLK_AIUS_L,
70 ASI_SCRATCHPAD = 0x20,
71 ASI_MMU = 0x21,
72 ASI_LDTX_AIUP = 0x22,
73 ASI_LD_TWINX_AS_IF_USER_PRIMARY = ASI_LDTX_AIUP,
74 ASI_LDTX_AIUS = 0x23,
75 ASI_LD_TWINX_AS_IF_USER_SECONDARY = ASI_LDTX_AIUS,
76 ASI_QUAD_LDD = 0x24,
77 ASI_QUEUE = 0x25,
78 ASI_QUAD_LDD_REAL = 0x26,
79 ASI_LDTX_REAL = ASI_QUAD_LDD_REAL,
80 ASI_LDTX_N = 0x27,
81 ASI_LD_TWINX_NUCLEUS = ASI_LDTX_N,
82 ASI_ST_BLKINIT_NUCLEUS = ASI_LDTX_N,
83 ASI_STBI_N = ASI_LDTX_N,
84 //0x28-0x29 implementation dependent
85 ASI_LDTX_AIUP_L = 0x2A,
86 ASI_TWINX_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
87 ASI_ST_BLKINIT_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
88 ASI_STBI_AIUP_L = ASI_LDTX_AIUP_L,
89 ASI_LDTX_AIUS_L = 0x2B,
90 ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
91 ASI_ST_BLKINIT_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
92 ASI_STBI_AIUS_L = ASI_LDTX_AIUS_L,
93 ASI_LTX_L = 0x2C,
94 ASI_TWINX_LITTLE = ASI_LTX_L,
95 //0x2D implementation dependent
96 ASI_LDTX_REAL_L = 0x2E,
97 ASI_LD_TWINX_REAL_LITTLE = ASI_LDTX_REAL_L,
98 ASI_LDTX_NL = 0x2F,
99 ASI_LD_TWINX_NUCLEUS_LITTLE = ASI_LDTX_NL,
100 //0x20 implementation dependent
101 ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x31,
102 ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x32,
103 ASI_DMMU_CTXT_ZERO_CONFIG = 0x33,
104 //0x34 implementation dependent
105 ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x35,
106 ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x36,
107 ASI_IMMU_CTXT_ZERO_CONFIG = 0x37,
108 //0x38 implementation dependent
109 ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x39,
110 ASI_DMMU_CTXT_NONZERO_USB_BASE_PS1 = 0x3A,
111 ASI_DMMU_CTXT_NONZERO_CONFIG = 0x3B,
112 //0x3C implementation dependent
113 ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x3D,
114 ASI_IMMU_CTXT_NONZERO_USB_BASE_PS1 = 0x3E,
115 ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F,
116 ASI_STREAM_MA = 0x40,
117 //0x41 implementation dependent
118 ASI_SPARC_BIST_CONTROL = 0x42,
119 ASI_INST_MASK_REG = 0x42,
120 ASI_LSU_DIAG_REG = 0x42,
121 //0x43 implementation dependent
122 ASI_STM_CTL_REG = 0x44,
123 ASI_LSU_CONTROL_REG = 0x45,
124 ASI_DCACHE_DATA = 0x46,
125 ASI_DCACHE_TAG = 0x47,
126 ASI_INTR_DISPATCH_STATUS = 0x48,
127 ASI_INTR_RECEIVE = 0x49,
128 ASI_UPA_CONFIG_REGISTER = 0x4A,
129 ASI_SPARC_ERROR_EN_REG = 0x4B,
130 ASI_SPARC_ERROR_STATUS_REG = 0x4C,
131 ASI_SPARC_ERROR_ADDRESS_REG = 0x4D,
132 ASI_ECACHE_TAG_DATA = 0x4E,
133 ASI_HYP_SCRATCHPAD = 0x4F,
134 ASI_IMMU = 0x50,
135 ASI_IMMU_TSB_PS0_PTR_REG = 0x51,
136 ASI_IMMU_TSB_PS1_PTR_REG = 0x52,
137 //0x53 implementation dependent
138 ASI_ITLB_DATA_IN_REG = 0x54,
139 ASI_ITLB_DATA_ACCESS_REG = 0x55,
140 ASI_ITLB_TAG_READ_REG = 0x56,
141 ASI_IMMU_DEMAP = 0x57,
142 ASI_DMMU = 0x58,
143 ASI_DMMU_TSB_PS0_PTR_REG = 0x59,
144 ASI_DMMU_TSB_PS1_PTR_REG = 0x5A,
145 ASI_DMMU_TSB_DIRECT_PTR_REG = 0x5B,
146 ASI_DTLB_DATA_IN_REG = 0x5C,
147 ASI_DTLB_DATA_ACCESS_REG = 0x5D,
148 ASI_DTLB_TAG_READ_REG = 0x5E,
149 ASI_DMMU_DEMAP = 0x5F,
150 ASI_TLB_INVALIDATE_ALL = 0x60,
151 //0x61-0x62 implementation dependent
152 ASI_CMT_PER_STRAND = 0x63,
153 //0x64-0x65 implementation dependent
154 ASI_ICACHE_INSTR = 0x66,
155 ASI_ICACHE_TAG = 0x67,
156 //0x68-0x71 implementation dependent
157 ASI_SWVR_INTR_RECEIVE = 0x72,
158 ASI_SWVR_UDB_INTR_W = 0x73,
159 ASI_SWVR_UDB_INTR_R = 0x74,
160 //0x74-0x7F reserved
161 /* Unpriveleged ASIs */
162 ASI_P = 0x80,
163 ASI_PRIMARY = ASI_P,
164 ASI_S = 0x81,
165 ASI_SECONDARY = ASI_S,
166 ASI_PNF = 0x82,
167 ASI_PRIMARY_NO_FAULT = ASI_PNF,
168 ASI_SNF = 0x83,
--- 68 unchanged lines hidden (view full) ---
237 ASI_BLK_S = 0xF1,
238 ASI_BLOCK_SECONDARY = ASI_BLK_S,
239 //0xF2-0xF7 implementation dependent
240 ASI_BLK_PL = 0xF8,
241 ASI_BLOCK_PRIMARY_LITTLE = ASI_BLK_PL,
242 ASI_BLK_SL = 0xF9,
243 ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL,
244 //0xFA-0xFF implementation dependent
245 ASI_IMPLICIT = 0xFF,
246 MAX_ASI = 0xFF
247 };
248
249 //Functions that classify an asi
250 bool AsiIsBlock(ASI);
251 bool AsiIsPrimary(ASI);
252 bool AsiIsSecondary(ASI);
253 bool AsiIsNucleus(ASI);
--- 5 unchanged lines hidden (view full) ---
259 bool AsiIsPartialStore(ASI);
260 bool AsiIsFloatingLoad(ASI);
261 bool AsiIsNoFault(ASI);
262 bool AsiIsScratchPad(ASI);
263 bool AsiIsCmt(ASI);
264 bool AsiIsQueue(ASI);
265 bool AsiIsDtlb(ASI);
266 bool AsiIsMmu(ASI);
267 bool AsiIsUnPriv(ASI);
268 bool AsiIsPriv(ASI);
269 bool AsiIsHPriv(ASI);
270 bool AsiIsReg(ASI);
271
272};
273
274#endif // __ARCH_SPARC_ASI_HH__
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
--- 12 unchanged lines hidden (view full) ---
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32#ifndef __ARCH_SPARC_ASI_HH__
33#define __ARCH_SPARC_ASI_HH__
34
35namespace SparcISA
36{
37 enum ASI {
--- 11 unchanged lines hidden (view full) ---
49 ASI_AS_IF_USER_SECONDARY = ASI_AIUS,
50 //0x12-0x13 implementation dependent
51 ASI_REAL = 0x14,
52 ASI_REAL_IO = 0x15,
53 ASI_BLK_AIUP = 0x16,
54 ASI_BLOCK_AS_IF_USER_PRIMARY = ASI_BLK_AIUP,
55 ASI_BLK_AIUS = 0x17,
56 ASI_BLOCK_AS_IF_USER_SECONDARY = ASI_BLK_AIUS,
57 ASI_AIUP_L = 0x18,
58 ASI_AS_IF_USER_PRIMARY_LITTLE = ASI_AIUP_L,
59 ASI_AIUS_L = 0x19,
60 ASI_AS_IF_USER_SECONDARY_LITTLE = ASI_AIUS_L,
61 //0x1A-0x1B implementation dependent
62 ASI_REAL_L = 0x1C,
63 ASI_REAL_LITTLE = ASI_REAL_L,
64 ASI_REAL_IO_L = 0x1D,
65 ASI_REAL_IO_LITTLE = ASI_REAL_IO_L,
66 ASI_BLK_AIUP_L = 0x1E,
67 ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = ASI_BLK_AIUP_L,
68 ASI_BLK_AIUS_L = 0x1F,
69 ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = ASI_BLK_AIUS_L,
70 ASI_SCRATCHPAD = 0x20,
71 ASI_MMU = 0x21,
72 ASI_LDTX_AIUP = 0x22,
73 ASI_LD_TWINX_AS_IF_USER_PRIMARY = ASI_LDTX_AIUP,
74 ASI_LDTX_AIUS = 0x23,
75 ASI_LD_TWINX_AS_IF_USER_SECONDARY = ASI_LDTX_AIUS,
76 ASI_QUAD_LDD = 0x24,
77 ASI_QUEUE = 0x25,
78 ASI_QUAD_LDD_REAL = 0x26,
79 ASI_LDTX_REAL = ASI_QUAD_LDD_REAL,
80 ASI_LDTX_N = 0x27,
81 ASI_LD_TWINX_NUCLEUS = ASI_LDTX_N,
82 ASI_ST_BLKINIT_NUCLEUS = ASI_LDTX_N,
83 ASI_STBI_N = ASI_LDTX_N,
84 //0x28-0x29 implementation dependent
85 ASI_LDTX_AIUP_L = 0x2A,
86 ASI_TWINX_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
87 ASI_ST_BLKINIT_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
88 ASI_STBI_AIUP_L = ASI_LDTX_AIUP_L,
89 ASI_LDTX_AIUS_L = 0x2B,
90 ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
91 ASI_ST_BLKINIT_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
92 ASI_STBI_AIUS_L = ASI_LDTX_AIUS_L,
93 ASI_LTX_L = 0x2C,
94 ASI_TWINX_LITTLE = ASI_LTX_L,
95 //0x2D implementation dependent
96 ASI_LDTX_REAL_L = 0x2E,
97 ASI_LD_TWINX_REAL_LITTLE = ASI_LDTX_REAL_L,
98 ASI_LDTX_NL = 0x2F,
99 ASI_LD_TWINX_NUCLEUS_LITTLE = ASI_LDTX_NL,
100 //0x20 implementation dependent
101 ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x31,
102 ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x32,
103 ASI_DMMU_CTXT_ZERO_CONFIG = 0x33,
104 //0x34 implementation dependent
105 ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x35,
106 ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x36,
107 ASI_IMMU_CTXT_ZERO_CONFIG = 0x37,
108 //0x38 implementation dependent
109 ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x39,
110 ASI_DMMU_CTXT_NONZERO_USB_BASE_PS1 = 0x3A,
111 ASI_DMMU_CTXT_NONZERO_CONFIG = 0x3B,
112 //0x3C implementation dependent
113 ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x3D,
114 ASI_IMMU_CTXT_NONZERO_USB_BASE_PS1 = 0x3E,
115 ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F,
116 ASI_STREAM_MA = 0x40,
117 //0x41 implementation dependent
118 ASI_SPARC_BIST_CONTROL = 0x42,
119 ASI_INST_MASK_REG = 0x42,
120 ASI_LSU_DIAG_REG = 0x42,
121 //0x43 implementation dependent
122 ASI_STM_CTL_REG = 0x44,
123 ASI_LSU_CONTROL_REG = 0x45,
124 ASI_DCACHE_DATA = 0x46,
125 ASI_DCACHE_TAG = 0x47,
126 ASI_INTR_DISPATCH_STATUS = 0x48,
127 ASI_INTR_RECEIVE = 0x49,
128 ASI_UPA_CONFIG_REGISTER = 0x4A,
129 ASI_SPARC_ERROR_EN_REG = 0x4B,
130 ASI_SPARC_ERROR_STATUS_REG = 0x4C,
131 ASI_SPARC_ERROR_ADDRESS_REG = 0x4D,
132 ASI_ECACHE_TAG_DATA = 0x4E,
133 ASI_HYP_SCRATCHPAD = 0x4F,
134 ASI_IMMU = 0x50,
135 ASI_IMMU_TSB_PS0_PTR_REG = 0x51,
136 ASI_IMMU_TSB_PS1_PTR_REG = 0x52,
137 //0x53 implementation dependent
138 ASI_ITLB_DATA_IN_REG = 0x54,
139 ASI_ITLB_DATA_ACCESS_REG = 0x55,
140 ASI_ITLB_TAG_READ_REG = 0x56,
141 ASI_IMMU_DEMAP = 0x57,
142 ASI_DMMU = 0x58,
143 ASI_DMMU_TSB_PS0_PTR_REG = 0x59,
144 ASI_DMMU_TSB_PS1_PTR_REG = 0x5A,
145 ASI_DMMU_TSB_DIRECT_PTR_REG = 0x5B,
146 ASI_DTLB_DATA_IN_REG = 0x5C,
147 ASI_DTLB_DATA_ACCESS_REG = 0x5D,
148 ASI_DTLB_TAG_READ_REG = 0x5E,
149 ASI_DMMU_DEMAP = 0x5F,
150 ASI_TLB_INVALIDATE_ALL = 0x60,
151 //0x61-0x62 implementation dependent
152 ASI_CMT_PER_STRAND = 0x63,
153 //0x64-0x65 implementation dependent
154 ASI_ICACHE_INSTR = 0x66,
155 ASI_ICACHE_TAG = 0x67,
156 //0x68-0x71 implementation dependent
157 ASI_SWVR_INTR_RECEIVE = 0x72,
158 ASI_SWVR_UDB_INTR_W = 0x73,
159 ASI_SWVR_UDB_INTR_R = 0x74,
160 //0x74-0x7F reserved
161 /* Unpriveleged ASIs */
162 ASI_P = 0x80,
163 ASI_PRIMARY = ASI_P,
164 ASI_S = 0x81,
165 ASI_SECONDARY = ASI_S,
166 ASI_PNF = 0x82,
167 ASI_PRIMARY_NO_FAULT = ASI_PNF,
168 ASI_SNF = 0x83,
--- 68 unchanged lines hidden (view full) ---
237 ASI_BLK_S = 0xF1,
238 ASI_BLOCK_SECONDARY = ASI_BLK_S,
239 //0xF2-0xF7 implementation dependent
240 ASI_BLK_PL = 0xF8,
241 ASI_BLOCK_PRIMARY_LITTLE = ASI_BLK_PL,
242 ASI_BLK_SL = 0xF9,
243 ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL,
244 //0xFA-0xFF implementation dependent
245 ASI_IMPLICIT = 0xFF,
246 MAX_ASI = 0xFF
247 };
248
249 //Functions that classify an asi
250 bool AsiIsBlock(ASI);
251 bool AsiIsPrimary(ASI);
252 bool AsiIsSecondary(ASI);
253 bool AsiIsNucleus(ASI);
--- 5 unchanged lines hidden (view full) ---
259 bool AsiIsPartialStore(ASI);
260 bool AsiIsFloatingLoad(ASI);
261 bool AsiIsNoFault(ASI);
262 bool AsiIsScratchPad(ASI);
263 bool AsiIsCmt(ASI);
264 bool AsiIsQueue(ASI);
265 bool AsiIsDtlb(ASI);
266 bool AsiIsMmu(ASI);
267 bool AsiIsUnPriv(ASI);
268 bool AsiIsPriv(ASI);
269 bool AsiIsHPriv(ASI);
270 bool AsiIsReg(ASI);
271
272};
273
274#endif // __ARCH_SPARC_ASI_HH__