decoder.isa (12807:0baf4adc1a45) decoder.isa (12849:7f43ad13ebf0)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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38 0x0: decode COPCODE {
39 0x0: CIOp::c_addi4spn({{
40 imm = CIMM8<1:1> << 2 |
41 CIMM8<0:0> << 3 |
42 CIMM8<7:6> << 4 |
43 CIMM8<5:2> << 6;
44 }}, {{
45 if (machInst == 0)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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38 0x0: decode COPCODE {
39 0x0: CIOp::c_addi4spn({{
40 imm = CIMM8<1:1> << 2 |
41 CIMM8<0:0> << 3 |
42 CIMM8<7:6> << 4 |
43 CIMM8<5:2> << 6;
44 }}, {{
45 if (machInst == 0)
46 fault = make_shared<IllegalInstFault>("zero instruction");
46 fault = make_shared<IllegalInstFault>("zero instruction",
47 machInst);
47 Rp2 = sp + imm;
48 }}, uint64_t);
49 format CompressedLoad {
50 0x1: c_fld({{
51 offset = CIMM3 << 3 | CIMM2 << 6;
52 }}, {{
53 Fp2_bits = Mem;
54 }}, {{

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101 format CIOp {
102 0x0: c_addi({{
103 imm = CIMM5;
104 if (CIMM1 > 0)
105 imm |= ~((uint64_t)0x1F);
106 }}, {{
107 if ((RC1 == 0) != (imm == 0)) {
108 if (RC1 == 0) {
48 Rp2 = sp + imm;
49 }}, uint64_t);
50 format CompressedLoad {
51 0x1: c_fld({{
52 offset = CIMM3 << 3 | CIMM2 << 6;
53 }}, {{
54 Fp2_bits = Mem;
55 }}, {{

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102 format CIOp {
103 0x0: c_addi({{
104 imm = CIMM5;
105 if (CIMM1 > 0)
106 imm |= ~((uint64_t)0x1F);
107 }}, {{
108 if ((RC1 == 0) != (imm == 0)) {
109 if (RC1 == 0) {
109 fault = make_shared<IllegalInstFault>("source reg x0");
110 fault = make_shared<IllegalInstFault>("source reg x0",
111 machInst);
110 } else // imm == 0
112 } else // imm == 0
111 fault = make_shared<IllegalInstFault>("immediate = 0");
113 fault = make_shared<IllegalInstFault>("immediate = 0",
114 machInst);
112 }
113 Rc1_sd = Rc1_sd + imm;
114 }});
115 0x1: c_addiw({{
116 imm = CIMM5;
117 if (CIMM1 > 0)
118 imm |= ~((uint64_t)0x1F);
119 }}, {{
120 if (RC1 == 0) {
115 }
116 Rc1_sd = Rc1_sd + imm;
117 }});
118 0x1: c_addiw({{
119 imm = CIMM5;
120 if (CIMM1 > 0)
121 imm |= ~((uint64_t)0x1F);
122 }}, {{
123 if (RC1 == 0) {
121 fault = make_shared<IllegalInstFault>("source reg x0");
124 fault = make_shared<IllegalInstFault>("source reg x0",
125 machInst);
122 }
123 Rc1_sd = (int32_t)Rc1_sd + imm;
124 }});
125 0x2: c_li({{
126 imm = CIMM5;
127 if (CIMM1 > 0)
128 imm |= ~((uint64_t)0x1F);
129 }}, {{
130 if (RC1 == 0) {
126 }
127 Rc1_sd = (int32_t)Rc1_sd + imm;
128 }});
129 0x2: c_li({{
130 imm = CIMM5;
131 if (CIMM1 > 0)
132 imm |= ~((uint64_t)0x1F);
133 }}, {{
134 if (RC1 == 0) {
131 fault = make_shared<IllegalInstFault>("source reg x0");
135 fault = make_shared<IllegalInstFault>("source reg x0",
136 machInst);
132 }
133 Rc1_sd = imm;
134 }});
135 0x3: decode RC1 {
136 0x2: c_addi16sp({{
137 imm = CIMM5<4:4> << 4 |
138 CIMM5<0:0> << 5 |
139 CIMM5<3:3> << 6 |
140 CIMM5<2:1> << 7;
141 if (CIMM1 > 0)
142 imm |= ~((int64_t)0x1FF);
143 }}, {{
144 if (imm == 0) {
137 }
138 Rc1_sd = imm;
139 }});
140 0x3: decode RC1 {
141 0x2: c_addi16sp({{
142 imm = CIMM5<4:4> << 4 |
143 CIMM5<0:0> << 5 |
144 CIMM5<3:3> << 6 |
145 CIMM5<2:1> << 7;
146 if (CIMM1 > 0)
147 imm |= ~((int64_t)0x1FF);
148 }}, {{
149 if (imm == 0) {
145 fault = make_shared<IllegalInstFault>("immediate = 0");
150 fault = make_shared<IllegalInstFault>("immediate = 0",
151 machInst);
146 }
147 sp_sd = sp_sd + imm;
148 }});
149 default: c_lui({{
150 imm = CIMM5 << 12;
151 if (CIMM1 > 0)
152 imm |= ~((uint64_t)0x1FFFF);
153 }}, {{
154 if (RC1 == 0 || RC1 == 2) {
152 }
153 sp_sd = sp_sd + imm;
154 }});
155 default: c_lui({{
156 imm = CIMM5 << 12;
157 if (CIMM1 > 0)
158 imm |= ~((uint64_t)0x1FFFF);
159 }}, {{
160 if (RC1 == 0 || RC1 == 2) {
155 fault = make_shared<IllegalInstFault>("source reg x0");
161 fault = make_shared<IllegalInstFault>("source reg x0",
162 machInst);
156 }
157 if (imm == 0) {
163 }
164 if (imm == 0) {
158 fault = make_shared<IllegalInstFault>("immediate = 0");
165 fault = make_shared<IllegalInstFault>("immediate = 0",
166 machInst);
159 }
160 Rc1_sd = imm;
161 }});
162 }
163 }
164 0x4: decode CFUNCT2HIGH {
165 format CIOp {
166 0x0: c_srli({{
167 imm = CIMM5 | (CIMM1 << 5);
168 }}, {{
169 if (imm == 0) {
167 }
168 Rc1_sd = imm;
169 }});
170 }
171 }
172 0x4: decode CFUNCT2HIGH {
173 format CIOp {
174 0x0: c_srli({{
175 imm = CIMM5 | (CIMM1 << 5);
176 }}, {{
177 if (imm == 0) {
170 fault = make_shared<IllegalInstFault>("immediate = 0");
178 fault = make_shared<IllegalInstFault>("immediate = 0",
179 machInst);
171 }
172 Rp1 = Rp1 >> imm;
173 }}, uint64_t);
174 0x1: c_srai({{
175 imm = CIMM5 | (CIMM1 << 5);
176 }}, {{
177 if (imm == 0) {
180 }
181 Rp1 = Rp1 >> imm;
182 }}, uint64_t);
183 0x1: c_srai({{
184 imm = CIMM5 | (CIMM1 << 5);
185 }}, {{
186 if (imm == 0) {
178 fault = make_shared<IllegalInstFault>("immediate = 0");
187 fault = make_shared<IllegalInstFault>("immediate = 0",
188 machInst);
179 }
180 Rp1_sd = Rp1_sd >> imm;
181 }}, uint64_t);
182 0x2: c_andi({{
183 imm = CIMM5;
184 if (CIMM1 > 0)
185 imm |= ~((uint64_t)0x1F);
186 }}, {{

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241 }}, IsDirectControl, IsCondControl);
242 }
243 }
244 0x2: decode COPCODE {
245 0x0: CIOp::c_slli({{
246 imm = CIMM5 | (CIMM1 << 5);
247 }}, {{
248 if (imm == 0) {
189 }
190 Rp1_sd = Rp1_sd >> imm;
191 }}, uint64_t);
192 0x2: c_andi({{
193 imm = CIMM5;
194 if (CIMM1 > 0)
195 imm |= ~((uint64_t)0x1F);
196 }}, {{

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251 }}, IsDirectControl, IsCondControl);
252 }
253 }
254 0x2: decode COPCODE {
255 0x0: CIOp::c_slli({{
256 imm = CIMM5 | (CIMM1 << 5);
257 }}, {{
258 if (imm == 0) {
249 fault = make_shared<IllegalInstFault>("immediate = 0");
259 fault = make_shared<IllegalInstFault>("immediate = 0",
260 machInst);
250 }
251 if (RC1 == 0) {
261 }
262 if (RC1 == 0) {
252 fault = make_shared<IllegalInstFault>("source reg x0");
263 fault = make_shared<IllegalInstFault>("source reg x0",
264 machInst);
253 }
254 Rc1 = Rc1 << imm;
255 }}, uint64_t);
256 format CompressedLoad {
257 0x1: c_fldsp({{
258 offset = CIMM5<4:3> << 3 |
259 CIMM1 << 5 |
260 CIMM5<2:0> << 6;
261 }}, {{
262 Fc1_bits = Mem;
263 }}, {{
264 EA = sp + offset;
265 }});
266 0x2: c_lwsp({{
267 offset = CIMM5<4:2> << 2 |
268 CIMM1 << 5 |
269 CIMM5<1:0> << 6;
270 }}, {{
271 if (RC1 == 0) {
265 }
266 Rc1 = Rc1 << imm;
267 }}, uint64_t);
268 format CompressedLoad {
269 0x1: c_fldsp({{
270 offset = CIMM5<4:3> << 3 |
271 CIMM1 << 5 |
272 CIMM5<2:0> << 6;
273 }}, {{
274 Fc1_bits = Mem;
275 }}, {{
276 EA = sp + offset;
277 }});
278 0x2: c_lwsp({{
279 offset = CIMM5<4:2> << 2 |
280 CIMM1 << 5 |
281 CIMM5<1:0> << 6;
282 }}, {{
283 if (RC1 == 0) {
272 fault = make_shared<IllegalInstFault>("source reg x0");
284 fault = make_shared<IllegalInstFault>("source reg x0",
285 machInst);
273 }
274 Rc1_sd = Mem_sw;
275 }}, {{
276 EA = sp + offset;
277 }});
278 0x3: c_ldsp({{
279 offset = CIMM5<4:3> << 3 |
280 CIMM1 << 5 |
281 CIMM5<2:0> << 6;
282 }}, {{
283 if (RC1 == 0) {
286 }
287 Rc1_sd = Mem_sw;
288 }}, {{
289 EA = sp + offset;
290 }});
291 0x3: c_ldsp({{
292 offset = CIMM5<4:3> << 3 |
293 CIMM1 << 5 |
294 CIMM5<2:0> << 6;
295 }}, {{
296 if (RC1 == 0) {
284 fault = make_shared<IllegalInstFault>("source reg x0");
297 fault = make_shared<IllegalInstFault>("source reg x0",
298 machInst);
285 }
286 Rc1_sd = Mem_sd;
287 }}, {{
288 EA = sp + offset;
289 }});
290 }
291 0x4: decode CFUNCT1 {
292 0x0: decode RC2 {
293 0x0: Jump::c_jr({{
294 if (RC1 == 0) {
299 }
300 Rc1_sd = Mem_sd;
301 }}, {{
302 EA = sp + offset;
303 }});
304 }
305 0x4: decode CFUNCT1 {
306 0x0: decode RC2 {
307 0x0: Jump::c_jr({{
308 if (RC1 == 0) {
295 fault = make_shared<IllegalInstFault>("source reg x0");
309 fault = make_shared<IllegalInstFault>("source reg x0",
310 machInst);
296 }
297 NPC = Rc1;
298 }}, IsIndirectControl, IsUncondControl, IsCall);
299 default: CROp::c_mv({{
300 if (RC1 == 0) {
311 }
312 NPC = Rc1;
313 }}, IsIndirectControl, IsUncondControl, IsCall);
314 default: CROp::c_mv({{
315 if (RC1 == 0) {
301 fault = make_shared<IllegalInstFault>("source reg x0");
316 fault = make_shared<IllegalInstFault>("source reg x0",
317 machInst);
302 }
303 Rc1 = Rc2;
304 }});
305 }
306 0x1: decode RC1 {
307 0x0: SystemOp::c_ebreak({{
308 if (RC2 != 0) {
318 }
319 Rc1 = Rc2;
320 }});
321 }
322 0x1: decode RC1 {
323 0x0: SystemOp::c_ebreak({{
324 if (RC2 != 0) {
309 fault = make_shared<IllegalInstFault>("source reg x1");
325 fault = make_shared<IllegalInstFault>("source reg x1",
326 machInst);
310 }
327 }
311 fault = make_shared();
328 fault = make_shared<BreakpointFault>(xc->pcState());
312 }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
313 default: decode RC2 {
314 0x0: Jump::c_jalr({{
315 if (RC1 == 0) {
316 fault = make_shared<IllegalInstFault>
329 }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
330 default: decode RC2 {
331 0x0: Jump::c_jalr({{
332 if (RC1 == 0) {
333 fault = make_shared<IllegalInstFault>
317 ("source reg x0");
334 ("source reg x0",
335 machInst);
318 }
319 ra = NPC;
320 NPC = Rc1;
321 }}, IsIndirectControl, IsUncondControl, IsCall);
322 default: ROp::c_add({{
323 Rc1_sd = Rc1_sd + Rc2_sd;
324 }});
325 }

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1245 FFLAGS |= FloatInvalid;
1246 } else {
1247 Fd = fmax(Fs1, Fs2);
1248 }
1249 }}, FloatCmpOp);
1250 }
1251 0x20: fcvt_s_d({{
1252 if (CONV_SGN != 1) {
336 }
337 ra = NPC;
338 NPC = Rc1;
339 }}, IsIndirectControl, IsUncondControl, IsCall);
340 default: ROp::c_add({{
341 Rc1_sd = Rc1_sd + Rc2_sd;
342 }});
343 }

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1263 FFLAGS |= FloatInvalid;
1264 } else {
1265 Fd = fmax(Fs1, Fs2);
1266 }
1267 }}, FloatCmpOp);
1268 }
1269 0x20: fcvt_s_d({{
1270 if (CONV_SGN != 1) {
1253 fault = make_shared<IllegalInstFault>("CONV_SGN != 1");
1271 fault = make_shared<IllegalInstFault>("CONV_SGN != 1",
1272 machInst);
1254 }
1255 float fd;
1256 if (issignalingnan(Fs1)) {
1257 fd = numeric_limits<float>::quiet_NaN();
1258 FFLAGS |= FloatInvalid;
1259 } else {
1260 fd = (float)Fs1;
1261 }
1262 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1263 }}, FloatCvtOp);
1264 0x21: fcvt_d_s({{
1265 if (CONV_SGN != 0) {
1273 }
1274 float fd;
1275 if (issignalingnan(Fs1)) {
1276 fd = numeric_limits<float>::quiet_NaN();
1277 FFLAGS |= FloatInvalid;
1278 } else {
1279 fd = (float)Fs1;
1280 }
1281 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1282 }}, FloatCvtOp);
1283 0x21: fcvt_d_s({{
1284 if (CONV_SGN != 0) {
1266 fault = make_shared<IllegalInstFault>("CONV_SGN != 0");
1285 fault = make_shared<IllegalInstFault>("CONV_SGN != 0",
1286 machInst);
1267 }
1268 uint32_t temp;
1269 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1270
1271 if (issignalingnan(fs1)) {
1272 Fd = numeric_limits<double>::quiet_NaN();
1273 FFLAGS |= FloatInvalid;
1274 } else {
1275 Fd = (double)fs1;
1276 }
1277 }}, FloatCvtOp);
1278 0x2c: fsqrt_s({{
1279 if (RS2 != 0) {
1287 }
1288 uint32_t temp;
1289 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1290
1291 if (issignalingnan(fs1)) {
1292 Fd = numeric_limits<double>::quiet_NaN();
1293 FFLAGS |= FloatInvalid;
1294 } else {
1295 Fd = (double)fs1;
1296 }
1297 }}, FloatCvtOp);
1298 0x2c: fsqrt_s({{
1299 if (RS2 != 0) {
1280 fault = make_shared<IllegalInstFault>("source reg x1");
1300 fault = make_shared<IllegalInstFault>("source reg x1",
1301 machInst);
1281 }
1282 uint32_t temp;
1283 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1284 float fd;
1285
1286 if (issignalingnan(Fs1_sf)) {
1287 FFLAGS |= FloatInvalid;
1288 }
1289 fd = sqrt(fs1);
1290 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1291 }}, FloatSqrtOp);
1292 0x2d: fsqrt_d({{
1293 if (RS2 != 0) {
1302 }
1303 uint32_t temp;
1304 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1305 float fd;
1306
1307 if (issignalingnan(Fs1_sf)) {
1308 FFLAGS |= FloatInvalid;
1309 }
1310 fd = sqrt(fs1);
1311 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1312 }}, FloatSqrtOp);
1313 0x2d: fsqrt_d({{
1314 if (RS2 != 0) {
1294 fault = make_shared<IllegalInstFault>("source reg x1");
1315 fault = make_shared<IllegalInstFault>("source reg x1",
1316 machInst);
1295 }
1296 Fd = sqrt(Fs1);
1297 }}, FloatSqrtOp);
1298 0x50: decode ROUND_MODE {
1299 0x0: fle_s({{
1300 uint32_t temp;
1301 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1302 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);

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1685 0x1c: decode FUNCT3 {
1686 format SystemOp {
1687 0x0: decode FUNCT12 {
1688 0x0: ecall({{
1689 fault = make_shared<SyscallFault>();
1690 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall,
1691 No_OpClass);
1692 0x1: ebreak({{
1317 }
1318 Fd = sqrt(Fs1);
1319 }}, FloatSqrtOp);
1320 0x50: decode ROUND_MODE {
1321 0x0: fle_s({{
1322 uint32_t temp;
1323 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1324 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);

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1707 0x1c: decode FUNCT3 {
1708 format SystemOp {
1709 0x0: decode FUNCT12 {
1710 0x0: ecall({{
1711 fault = make_shared<SyscallFault>();
1712 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall,
1713 No_OpClass);
1714 0x1: ebreak({{
1693 fault = make_shared();
1715 fault = make_shared<BreakpointFault>(xc->pcState());
1694 }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
1695 0x100: eret({{
1716 }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
1717 0x100: eret({{
1696 fault = make_shared<UnimplementedFault>("eret");
1718 fault = make_shared<UnimplementedFault>("eret",
1719 machInst);
1697 }}, No_OpClass);
1698 }
1699 }
1700 format CSROp {
1701 0x1: csrrw({{
1702 Rd = data;
1703 data = Rs1;
1704 }}, IsNonSpeculative, No_OpClass);

--- 24 unchanged lines hidden --- 		1720 }}, No_OpClass);
1721 }
1722 }
1723 format CSROp {
1724 0x1: csrrw({{
1725 Rd = data;
1726 data = Rs1;
1727 }}, IsNonSpeculative, No_OpClass);

--- 24 unchanged lines hidden ---