decoder.isa (12535:22fe7cd9a852) decoder.isa (12596:5102ba06fca5)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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112 }
113 Rc1_sd = Rc1_sd + imm;
114 }});
115 0x1: c_addiw({{
116 imm = CIMM5;
117 if (CIMM1 > 0)
118 imm |= ~((uint64_t)0x1F);
119 }}, {{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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112 }
113 Rc1_sd = Rc1_sd + imm;
114 }});
115 0x1: c_addiw({{
116 imm = CIMM5;
117 if (CIMM1 > 0)
118 imm |= ~((uint64_t)0x1F);
119 }}, {{
120 assert(RC1 != 0);
120 if (RC1 == 0) {
121 fault = make_shared<IllegalInstFault>("source reg x0");
122 }
121 Rc1_sd = (int32_t)Rc1_sd + imm;
122 }});
123 0x2: c_li({{
124 imm = CIMM5;
125 if (CIMM1 > 0)
126 imm |= ~((uint64_t)0x1F);
127 }}, {{
123 Rc1_sd = (int32_t)Rc1_sd + imm;
124 }});
125 0x2: c_li({{
126 imm = CIMM5;
127 if (CIMM1 > 0)
128 imm |= ~((uint64_t)0x1F);
129 }}, {{
128 assert(RC1 != 0);
130 if (RC1 == 0) {
131 fault = make_shared<IllegalInstFault>("source reg x0");
132 }
129 Rc1_sd = imm;
130 }});
131 0x3: decode RC1 {
132 0x2: c_addi16sp({{
133 imm = CIMM5<4:4> << 4 |
134 CIMM5<0:0> << 5 |
135 CIMM5<3:3> << 6 |
136 CIMM5<2:1> << 7;
137 if (CIMM1 > 0)
138 imm |= ~((int64_t)0x1FF);
139 }}, {{
133 Rc1_sd = imm;
134 }});
135 0x3: decode RC1 {
136 0x2: c_addi16sp({{
137 imm = CIMM5<4:4> << 4 |
138 CIMM5<0:0> << 5 |
139 CIMM5<3:3> << 6 |
140 CIMM5<2:1> << 7;
141 if (CIMM1 > 0)
142 imm |= ~((int64_t)0x1FF);
143 }}, {{
140 assert(imm != 0);
144 if (imm == 0) {
145 fault = make_shared<IllegalInstFault>("immediate = 0");
146 }
141 sp_sd = sp_sd + imm;
142 }});
143 default: c_lui({{
144 imm = CIMM5 << 12;
145 if (CIMM1 > 0)
146 imm |= ~((uint64_t)0x1FFFF);
147 }}, {{
147 sp_sd = sp_sd + imm;
148 }});
149 default: c_lui({{
150 imm = CIMM5 << 12;
151 if (CIMM1 > 0)
152 imm |= ~((uint64_t)0x1FFFF);
153 }}, {{
148 assert(RC1 != 0 && RC1 != 2);
149 assert(imm != 0);
154 if (RC1 == 0 || RC1 == 2) {
155 fault = make_shared<IllegalInstFault>("source reg x0");
156 }
157 if (imm == 0) {
158 fault = make_shared<IllegalInstFault>("immediate = 0");
159 }
150 Rc1_sd = imm;
151 }});
152 }
153 }
154 0x4: decode CFUNCT2HIGH {
155 format CIOp {
156 0x0: c_srli({{
157 imm = CIMM5 | (CIMM1 << 5);
160 Rc1_sd = imm;
161 }});
162 }
163 }
164 0x4: decode CFUNCT2HIGH {
165 format CIOp {
166 0x0: c_srli({{
167 imm = CIMM5 | (CIMM1 << 5);
158 assert(imm != 0);
159 }}, {{
168 }}, {{
169 if (imm == 0) {
170 fault = make_shared<IllegalInstFault>("immediate = 0");
171 }
160 Rp1 = Rp1 >> imm;
161 }}, uint64_t);
162 0x1: c_srai({{
163 imm = CIMM5 | (CIMM1 << 5);
172 Rp1 = Rp1 >> imm;
173 }}, uint64_t);
174 0x1: c_srai({{
175 imm = CIMM5 | (CIMM1 << 5);
164 assert(imm != 0);
165 }}, {{
176 }}, {{
177 if (imm == 0) {
178 fault = make_shared<IllegalInstFault>("immediate = 0");
179 }
166 Rp1_sd = Rp1_sd >> imm;
167 }}, uint64_t);
168 0x2: c_andi({{
169 imm = CIMM5;
170 if (CIMM1 > 0)
171 imm |= ~((uint64_t)0x1F);
172 }}, {{
173 Rp1 = Rp1 & imm;

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225 else
226 NPC = NPC;
227 }}, IsDirectControl, IsCondControl);
228 }
229 }
230 0x2: decode COPCODE {
231 0x0: CIOp::c_slli({{
232 imm = CIMM5 | (CIMM1 << 5);
180 Rp1_sd = Rp1_sd >> imm;
181 }}, uint64_t);
182 0x2: c_andi({{
183 imm = CIMM5;
184 if (CIMM1 > 0)
185 imm |= ~((uint64_t)0x1F);
186 }}, {{
187 Rp1 = Rp1 & imm;

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239 else
240 NPC = NPC;
241 }}, IsDirectControl, IsCondControl);
242 }
243 }
244 0x2: decode COPCODE {
245 0x0: CIOp::c_slli({{
246 imm = CIMM5 | (CIMM1 << 5);
233 assert(imm != 0);
234 }}, {{
247 }}, {{
235 assert(RC1 != 0);
248 if (imm == 0) {
249 fault = make_shared<IllegalInstFault>("immediate = 0");
250 }
251 if (RC1 == 0) {
252 fault = make_shared<IllegalInstFault>("source reg x0");
253 }
236 Rc1 = Rc1 << imm;
237 }}, uint64_t);
238 format CompressedLoad {
239 0x1: c_fldsp({{
240 offset = CIMM5<4:3> << 3 |
241 CIMM1 << 5 |
242 CIMM5<2:0> << 6;
243 }}, {{
244 Fc1_bits = Mem;
245 }}, {{
246 EA = sp + offset;
247 }});
248 0x2: c_lwsp({{
249 offset = CIMM5<4:2> << 2 |
250 CIMM1 << 5 |
251 CIMM5<1:0> << 6;
252 }}, {{
254 Rc1 = Rc1 << imm;
255 }}, uint64_t);
256 format CompressedLoad {
257 0x1: c_fldsp({{
258 offset = CIMM5<4:3> << 3 |
259 CIMM1 << 5 |
260 CIMM5<2:0> << 6;
261 }}, {{
262 Fc1_bits = Mem;
263 }}, {{
264 EA = sp + offset;
265 }});
266 0x2: c_lwsp({{
267 offset = CIMM5<4:2> << 2 |
268 CIMM1 << 5 |
269 CIMM5<1:0> << 6;
270 }}, {{
253 assert(RC1 != 0);
271 if (RC1 == 0) {
272 fault = make_shared<IllegalInstFault>("source reg x0");
273 }
254 Rc1_sd = Mem_sw;
255 }}, {{
256 EA = sp + offset;
257 }});
258 0x3: c_ldsp({{
259 offset = CIMM5<4:3> << 3 |
260 CIMM1 << 5 |
261 CIMM5<2:0> << 6;
262 }}, {{
274 Rc1_sd = Mem_sw;
275 }}, {{
276 EA = sp + offset;
277 }});
278 0x3: c_ldsp({{
279 offset = CIMM5<4:3> << 3 |
280 CIMM1 << 5 |
281 CIMM5<2:0> << 6;
282 }}, {{
263 assert(RC1 != 0);
283 if (RC1 == 0) {
284 fault = make_shared<IllegalInstFault>("source reg x0");
285 }
264 Rc1_sd = Mem_sd;
265 }}, {{
266 EA = sp + offset;
267 }});
268 }
269 0x4: decode CFUNCT1 {
270 0x0: decode RC2 {
271 0x0: Jump::c_jr({{
286 Rc1_sd = Mem_sd;
287 }}, {{
288 EA = sp + offset;
289 }});
290 }
291 0x4: decode CFUNCT1 {
292 0x0: decode RC2 {
293 0x0: Jump::c_jr({{
272 assert(RC1 != 0);
294 if (RC1 == 0) {
295 fault = make_shared<IllegalInstFault>("source reg x0");
296 }
273 NPC = Rc1;
274 }}, IsIndirectControl, IsUncondControl, IsCall);
275 default: CROp::c_mv({{
297 NPC = Rc1;
298 }}, IsIndirectControl, IsUncondControl, IsCall);
299 default: CROp::c_mv({{
276 assert(RC1 != 0);
300 if (RC1 == 0) {
301 fault = make_shared<IllegalInstFault>("source reg x0");
302 }
277 Rc1 = Rc2;
278 }});
279 }
280 0x1: decode RC1 {
281 0x0: SystemOp::c_ebreak({{
303 Rc1 = Rc2;
304 }});
305 }
306 0x1: decode RC1 {
307 0x0: SystemOp::c_ebreak({{
282 assert(RC2 == 0);
308 if (RC2 != 0) {
309 fault = make_shared<IllegalInstFault>("source reg x1");
310 }
283 fault = make_shared<BreakpointFault>();
284 }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
285 default: decode RC2 {
286 0x0: Jump::c_jalr({{
311 fault = make_shared<BreakpointFault>();
312 }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
313 default: decode RC2 {
314 0x0: Jump::c_jalr({{
287 assert(RC1 != 0);
315 if (RC1 == 0) {
316 fault = make_shared<IllegalInstFault>
317 ("source reg x0");
318 }
288 ra = NPC;
289 NPC = Rc1;
290 }}, IsIndirectControl, IsUncondControl, IsCall);
291 default: ROp::c_add({{
292 Rc1_sd = Rc1_sd + Rc2_sd;
293 }});
294 }
295 }

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1213 Fd = Fs2;
1214 FFLAGS |= FloatInvalid;
1215 } else {
1216 Fd = fmax(Fs1, Fs2);
1217 }
1218 }}, FloatCmpOp);
1219 }
1220 0x20: fcvt_s_d({{
319 ra = NPC;
320 NPC = Rc1;
321 }}, IsIndirectControl, IsUncondControl, IsCall);
322 default: ROp::c_add({{
323 Rc1_sd = Rc1_sd + Rc2_sd;
324 }});
325 }
326 }

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1244 Fd = Fs2;
1245 FFLAGS |= FloatInvalid;
1246 } else {
1247 Fd = fmax(Fs1, Fs2);
1248 }
1249 }}, FloatCmpOp);
1250 }
1251 0x20: fcvt_s_d({{
1221 assert(CONV_SGN == 1);
1252 if (CONV_SGN != 1) {
1253 fault = make_shared<IllegalInstFault>("CONV_SGN != 1");
1254 }
1222 float fd;
1223 if (issignalingnan(Fs1)) {
1224 fd = numeric_limits<float>::quiet_NaN();
1225 FFLAGS |= FloatInvalid;
1226 } else {
1227 fd = (float)Fs1;
1228 }
1229 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1230 }}, FloatCvtOp);
1231 0x21: fcvt_d_s({{
1255 float fd;
1256 if (issignalingnan(Fs1)) {
1257 fd = numeric_limits<float>::quiet_NaN();
1258 FFLAGS |= FloatInvalid;
1259 } else {
1260 fd = (float)Fs1;
1261 }
1262 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1263 }}, FloatCvtOp);
1264 0x21: fcvt_d_s({{
1232 assert(CONV_SGN == 0);
1265 if (CONV_SGN != 0) {
1266 fault = make_shared<IllegalInstFault>("CONV_SGN != 0");
1267 }
1233 uint32_t temp;
1234 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1235
1236 if (issignalingnan(fs1)) {
1237 Fd = numeric_limits<double>::quiet_NaN();
1238 FFLAGS |= FloatInvalid;
1239 } else {
1240 Fd = (double)fs1;
1241 }
1242 }}, FloatCvtOp);
1243 0x2c: fsqrt_s({{
1268 uint32_t temp;
1269 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1270
1271 if (issignalingnan(fs1)) {
1272 Fd = numeric_limits<double>::quiet_NaN();
1273 FFLAGS |= FloatInvalid;
1274 } else {
1275 Fd = (double)fs1;
1276 }
1277 }}, FloatCvtOp);
1278 0x2c: fsqrt_s({{
1244 assert(RS2 == 0);
1279 if (RS2 != 0) {
1280 fault = make_shared<IllegalInstFault>("source reg x1");
1281 }
1245 uint32_t temp;
1246 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1247 float fd;
1248
1249 if (issignalingnan(Fs1_sf)) {
1250 FFLAGS |= FloatInvalid;
1251 }
1252 fd = sqrt(fs1);
1253 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1254 }}, FloatSqrtOp);
1255 0x2d: fsqrt_d({{
1282 uint32_t temp;
1283 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1284 float fd;
1285
1286 if (issignalingnan(Fs1_sf)) {
1287 FFLAGS |= FloatInvalid;
1288 }
1289 fd = sqrt(fs1);
1290 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1291 }}, FloatSqrtOp);
1292 0x2d: fsqrt_d({{
1256 assert(RS2 == 0);
1293 if (RS2 != 0) {
1294 fault = make_shared<IllegalInstFault>("source reg x1");
1295 }
1257 Fd = sqrt(Fs1);
1258 }}, FloatSqrtOp);
1259 0x50: decode ROUND_MODE {
1260 0x0: fle_s({{
1261 uint32_t temp;
1262 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1263 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1264

--- 433 unchanged lines hidden --- 		1296 Fd = sqrt(Fs1);
1297 }}, FloatSqrtOp);
1298 0x50: decode ROUND_MODE {
1299 0x0: fle_s({{
1300 uint32_t temp;
1301 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1302 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1303

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