decoder.isa (12444:06e9f1927cc7) decoder.isa (12445:cda4ad06d1ff)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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361 }});
362 }
363 }
364
365 0x01: decode FUNCT3 {
366 format Load {
367 0x2: flw({{
368 Fd_bits = (uint64_t)Mem_uw;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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361 }});
362 }
363 }
364
365 0x01: decode FUNCT3 {
366 format Load {
367 0x2: flw({{
368 Fd_bits = (uint64_t)Mem_uw;
369 }});
369 }}, inst_flags=FloatMemReadOp);
370 0x3: fld({{
371 Fd_bits = Mem;
370 0x3: fld({{
371 Fd_bits = Mem;
372 }});
372 }}, inst_flags=FloatMemReadOp);
373 }
374 }
375
376 0x03: decode FUNCT3 {
377 format IOp {
378 0x0: fence({{
379 }}, uint64_t, IsNonSpeculative, IsMemBarrier, No_OpClass);
380 0x1: fence_i({{

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455 }});
456 }
457 }
458
459 0x09: decode FUNCT3 {
460 format Store {
461 0x2: fsw({{
462 Mem_uw = (uint32_t)Fs2_bits;
373 }
374 }
375
376 0x03: decode FUNCT3 {
377 format IOp {
378 0x0: fence({{
379 }}, uint64_t, IsNonSpeculative, IsMemBarrier, No_OpClass);
380 0x1: fence_i({{

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455 }});
456 }
457 }
458
459 0x09: decode FUNCT3 {
460 format Store {
461 0x2: fsw({{
462 Mem_uw = (uint32_t)Fs2_bits;
463 }});
463 }}, inst_flags=FloatMemWriteOp);
464 0x3: fsd({{
465 Mem_ud = Fs2_bits;
464 0x3: fsd({{
465 Mem_ud = Fs2_bits;
466 }});
466 }}, inst_flags=FloatMemWriteOp);
467 }
468 }
469
470 0x0b: decode FUNCT3 {
471 0x2: decode AMOFUNCT {
472 0x2: LoadReserved::lr_w({{
473 Rd_sd = Mem_sw;
474 }}, mem_flags=LLSC);

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801 fd = -numeric_limits<float>::infinity();
802 } else { // Fs3_sf is infinity
803 fd = fs3;
804 }
805 } else {
806 fd = fs1*fs2 + fs3;
807 }
808 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
467 }
468 }
469
470 0x0b: decode FUNCT3 {
471 0x2: decode AMOFUNCT {
472 0x2: LoadReserved::lr_w({{
473 Rd_sd = Mem_sw;
474 }}, mem_flags=LLSC);

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801 fd = -numeric_limits<float>::infinity();
802 } else { // Fs3_sf is infinity
803 fd = fs3;
804 }
805 } else {
806 fd = fs1*fs2 + fs3;
807 }
808 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
809 }}, FloatMultOp);
809 }}, FloatMultAccOp);
810 0x1: fmadd_d({{
811 if (std::isnan(Fs1) || std::isnan(Fs2) ||
812 std::isnan(Fs3)) {
813 if (issignalingnan(Fs1) || issignalingnan(Fs2)
814 || issignalingnan(Fs3)) {
815 FFLAGS |= FloatInvalid;
816 }
817 Fd = numeric_limits<double>::quiet_NaN();

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824 && !std::isinf(Fs3)) {
825 Fd = -numeric_limits<double>::infinity();
826 } else {
827 Fd = Fs3;
828 }
829 } else {
830 Fd = Fs1*Fs2 + Fs3;
831 }
810 0x1: fmadd_d({{
811 if (std::isnan(Fs1) || std::isnan(Fs2) ||
812 std::isnan(Fs3)) {
813 if (issignalingnan(Fs1) || issignalingnan(Fs2)
814 || issignalingnan(Fs3)) {
815 FFLAGS |= FloatInvalid;
816 }
817 Fd = numeric_limits<double>::quiet_NaN();

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824 && !std::isinf(Fs3)) {
825 Fd = -numeric_limits<double>::infinity();
826 } else {
827 Fd = Fs3;
828 }
829 } else {
830 Fd = Fs1*Fs2 + Fs3;
831 }
832 }}, FloatMultOp);
832 }}, FloatMultAccOp);
833 }
834 0x11: decode FUNCT2 {
835 0x0: fmsub_s({{
836 uint32_t temp;
837 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
838 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
839 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
840 float fd;

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856 fd = -numeric_limits<float>::infinity();
857 } else { // Fs3_sf is infinity
858 fd = -fs3;
859 }
860 } else {
861 fd = fs1*fs2 - fs3;
862 }
863 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
833 }
834 0x11: decode FUNCT2 {
835 0x0: fmsub_s({{
836 uint32_t temp;
837 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
838 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
839 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
840 float fd;

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856 fd = -numeric_limits<float>::infinity();
857 } else { // Fs3_sf is infinity
858 fd = -fs3;
859 }
860 } else {
861 fd = fs1*fs2 - fs3;
862 }
863 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
864 }}, FloatMultOp);
864 }}, FloatMultAccOp);
865 0x1: fmsub_d({{
866 if (std::isnan(Fs1) || std::isnan(Fs2) ||
867 std::isnan(Fs3)) {
868 if (issignalingnan(Fs1) || issignalingnan(Fs2)
869 || issignalingnan(Fs3)) {
870 FFLAGS |= FloatInvalid;
871 }
872 Fd = numeric_limits<double>::quiet_NaN();

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879 && !std::isinf(Fs3)) {
880 Fd = -numeric_limits<double>::infinity();
881 } else {
882 Fd = -Fs3;
883 }
884 } else {
885 Fd = Fs1*Fs2 - Fs3;
886 }
865 0x1: fmsub_d({{
866 if (std::isnan(Fs1) || std::isnan(Fs2) ||
867 std::isnan(Fs3)) {
868 if (issignalingnan(Fs1) || issignalingnan(Fs2)
869 || issignalingnan(Fs3)) {
870 FFLAGS |= FloatInvalid;
871 }
872 Fd = numeric_limits<double>::quiet_NaN();

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879 && !std::isinf(Fs3)) {
880 Fd = -numeric_limits<double>::infinity();
881 } else {
882 Fd = -Fs3;
883 }
884 } else {
885 Fd = Fs1*Fs2 - Fs3;
886 }
887 }}, FloatMultOp);
887 }}, FloatMultAccOp);
888 }
889 0x12: decode FUNCT2 {
890 0x0: fnmsub_s({{
891 uint32_t temp;
892 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
893 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
894 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
895 float fd;

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911 fd = numeric_limits<float>::infinity();
912 } else { // Fs3_sf is infinity
913 fd = fs3;
914 }
915 } else {
916 fd = -(fs1*fs2 - fs3);
917 }
918 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
888 }
889 0x12: decode FUNCT2 {
890 0x0: fnmsub_s({{
891 uint32_t temp;
892 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
893 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
894 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
895 float fd;

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911 fd = numeric_limits<float>::infinity();
912 } else { // Fs3_sf is infinity
913 fd = fs3;
914 }
915 } else {
916 fd = -(fs1*fs2 - fs3);
917 }
918 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
919 }}, FloatMultOp);
919 }}, FloatMultAccOp);
920 0x1: fnmsub_d({{
921 if (std::isnan(Fs1) || std::isnan(Fs2) ||
922 std::isnan(Fs3)) {
923 if (issignalingnan(Fs1) || issignalingnan(Fs2)
924 || issignalingnan(Fs3)) {
925 FFLAGS |= FloatInvalid;
926 }
927 Fd = numeric_limits<double>::quiet_NaN();

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934 && !std::isinf(Fs3)) {
935 Fd = numeric_limits<double>::infinity();
936 } else {
937 Fd = Fs3;
938 }
939 } else {
940 Fd = -(Fs1*Fs2 - Fs3);
941 }
920 0x1: fnmsub_d({{
921 if (std::isnan(Fs1) || std::isnan(Fs2) ||
922 std::isnan(Fs3)) {
923 if (issignalingnan(Fs1) || issignalingnan(Fs2)
924 || issignalingnan(Fs3)) {
925 FFLAGS |= FloatInvalid;
926 }
927 Fd = numeric_limits<double>::quiet_NaN();

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934 && !std::isinf(Fs3)) {
935 Fd = numeric_limits<double>::infinity();
936 } else {
937 Fd = Fs3;
938 }
939 } else {
940 Fd = -(Fs1*Fs2 - Fs3);
941 }
942 }}, FloatMultOp);
942 }}, FloatMultAccOp);
943 }
944 0x13: decode FUNCT2 {
945 0x0: fnmadd_s({{
946 uint32_t temp;
947 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
948 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
949 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
950 float fd;

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966 fd = numeric_limits<float>::infinity();
967 } else { // Fs3_sf is infinity
968 fd = -fs3;
969 }
970 } else {
971 fd = -(fs1*fs2 + fs3);
972 }
973 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
943 }
944 0x13: decode FUNCT2 {
945 0x0: fnmadd_s({{
946 uint32_t temp;
947 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
948 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
949 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
950 float fd;

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966 fd = numeric_limits<float>::infinity();
967 } else { // Fs3_sf is infinity
968 fd = -fs3;
969 }
970 } else {
971 fd = -(fs1*fs2 + fs3);
972 }
973 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
974 }}, FloatMultOp);
974 }}, FloatMultAccOp);
975 0x1: fnmadd_d({{
976 if (std::isnan(Fs1) || std::isnan(Fs2) ||
977 std::isnan(Fs3)) {
978 if (issignalingnan(Fs1) || issignalingnan(Fs2)
979 || issignalingnan(Fs3)) {
980 FFLAGS |= FloatInvalid;
981 }
982 Fd = numeric_limits<double>::quiet_NaN();

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989 && !std::isinf(Fs3)) {
990 Fd = numeric_limits<double>::infinity();
991 } else {
992 Fd = -Fs3;
993 }
994 } else {
995 Fd = -(Fs1*Fs2 + Fs3);
996 }
975 0x1: fnmadd_d({{
976 if (std::isnan(Fs1) || std::isnan(Fs2) ||
977 std::isnan(Fs3)) {
978 if (issignalingnan(Fs1) || issignalingnan(Fs2)
979 || issignalingnan(Fs3)) {
980 FFLAGS |= FloatInvalid;
981 }
982 Fd = numeric_limits<double>::quiet_NaN();

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989 && !std::isinf(Fs3)) {
990 Fd = numeric_limits<double>::infinity();
991 } else {
992 Fd = -Fs3;
993 }
994 } else {
995 Fd = -(Fs1*Fs2 + Fs3);
996 }
997 }}, FloatMultOp);
997 }}, FloatMultAccOp);
998 }
999 0x14: decode FUNCT7 {
1000 0x0: fadd_s({{
1001 uint32_t temp;
1002 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1003 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1004 float fd;
1005

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1110
1111 if (issignalingnan(fs1)) {
1112 fd = numeric_limits<float>::signaling_NaN();
1113 feclearexcept(FE_INVALID);
1114 } else {
1115 fd = copysign(fs1, fs2);
1116 }
1117 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
998 }
999 0x14: decode FUNCT7 {
1000 0x0: fadd_s({{
1001 uint32_t temp;
1002 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1003 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1004 float fd;
1005

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1110
1111 if (issignalingnan(fs1)) {
1112 fd = numeric_limits<float>::signaling_NaN();
1113 feclearexcept(FE_INVALID);
1114 } else {
1115 fd = copysign(fs1, fs2);
1116 }
1117 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1118 }});
1118 }}, FloatMiscOp);
1119 0x1: fsgnjn_s({{
1120 uint32_t temp;
1121 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1122 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1123 float fd;
1124
1125 if (issignalingnan(fs1)) {
1126 fd = numeric_limits<float>::signaling_NaN();
1127 feclearexcept(FE_INVALID);
1128 } else {
1129 fd = copysign(fs1, -fs2);
1130 }
1131 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1119 0x1: fsgnjn_s({{
1120 uint32_t temp;
1121 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1122 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1123 float fd;
1124
1125 if (issignalingnan(fs1)) {
1126 fd = numeric_limits<float>::signaling_NaN();
1127 feclearexcept(FE_INVALID);
1128 } else {
1129 fd = copysign(fs1, -fs2);
1130 }
1131 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1132 }});
1132 }}, FloatMiscOp);
1133 0x2: fsgnjx_s({{
1134 uint32_t temp;
1135 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1136 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1137 float fd;
1138
1139 if (issignalingnan(fs1)) {
1140 fd = numeric_limits<float>::signaling_NaN();
1141 feclearexcept(FE_INVALID);
1142 } else {
1143 fd = fs1*(signbit(fs2) ? -1.0 : 1.0);
1144 }
1145 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1133 0x2: fsgnjx_s({{
1134 uint32_t temp;
1135 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1136 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1137 float fd;
1138
1139 if (issignalingnan(fs1)) {
1140 fd = numeric_limits<float>::signaling_NaN();
1141 feclearexcept(FE_INVALID);
1142 } else {
1143 fd = fs1*(signbit(fs2) ? -1.0 : 1.0);
1144 }
1145 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1146 }});
1146 }}, FloatMiscOp);
1147 }
1148 0x11: decode ROUND_MODE {
1149 0x0: fsgnj_d({{
1150 if (issignalingnan(Fs1)) {
1151 Fd = numeric_limits<double>::signaling_NaN();
1152 feclearexcept(FE_INVALID);
1153 } else {
1154 Fd = copysign(Fs1, Fs2);
1155 }
1147 }
1148 0x11: decode ROUND_MODE {
1149 0x0: fsgnj_d({{
1150 if (issignalingnan(Fs1)) {
1151 Fd = numeric_limits<double>::signaling_NaN();
1152 feclearexcept(FE_INVALID);
1153 } else {
1154 Fd = copysign(Fs1, Fs2);
1155 }
1156 }});
1156 }}, FloatMiscOp);
1157 0x1: fsgnjn_d({{
1158 if (issignalingnan(Fs1)) {
1159 Fd = numeric_limits<double>::signaling_NaN();
1160 feclearexcept(FE_INVALID);
1161 } else {
1162 Fd = copysign(Fs1, -Fs2);
1163 }
1157 0x1: fsgnjn_d({{
1158 if (issignalingnan(Fs1)) {
1159 Fd = numeric_limits<double>::signaling_NaN();
1160 feclearexcept(FE_INVALID);
1161 } else {
1162 Fd = copysign(Fs1, -Fs2);
1163 }
1164 }});
1164 }}, FloatMiscOp);
1165 0x2: fsgnjx_d({{
1166 if (issignalingnan(Fs1)) {
1167 Fd = numeric_limits<double>::signaling_NaN();
1168 feclearexcept(FE_INVALID);
1169 } else {
1170 Fd = Fs1*(signbit(Fs2) ? -1.0 : 1.0);
1171 }
1165 0x2: fsgnjx_d({{
1166 if (issignalingnan(Fs1)) {
1167 Fd = numeric_limits<double>::signaling_NaN();
1168 feclearexcept(FE_INVALID);
1169 } else {
1170 Fd = Fs1*(signbit(Fs2) ? -1.0 : 1.0);
1171 }
1172 }});
1172 }}, FloatMiscOp);
1173 }
1174 0x14: decode ROUND_MODE {
1175 0x0: fmin_s({{
1176 uint32_t temp;
1177 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1178 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1179 float fd;
1180

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1496 if ((Rd&0x80000000) != 0) {
1497 Rd |= (0xFFFFFFFFULL << 32);
1498 }
1499 }}, FloatCvtOp);
1500 0x1: fclass_s({{
1501 uint32_t temp;
1502 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1503 switch (fpclassify(fs1)) {
1173 }
1174 0x14: decode ROUND_MODE {
1175 0x0: fmin_s({{
1176 uint32_t temp;
1177 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1178 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1179 float fd;
1180

--- 315 unchanged lines hidden (view full) ---

1496 if ((Rd&0x80000000) != 0) {
1497 Rd |= (0xFFFFFFFFULL << 32);
1498 }
1499 }}, FloatCvtOp);
1500 0x1: fclass_s({{
1501 uint32_t temp;
1502 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1503 switch (fpclassify(fs1)) {
1504 case FP_INFINITE:
1504 case FP_INFINITE:
1505 if (signbit(fs1)) {
1506 Rd = 1 << 0;
1507 } else {
1508 Rd = 1 << 7;
1509 }
1510 break;
1505 if (signbit(fs1)) {
1506 Rd = 1 << 0;
1507 } else {
1508 Rd = 1 << 7;
1509 }
1510 break;
1511 case FP_NAN:
1511 case FP_NAN:
1512 if (issignalingnan(fs1)) {
1513 Rd = 1 << 8;
1514 } else {
1515 Rd = 1 << 9;
1516 }
1517 break;
1512 if (issignalingnan(fs1)) {
1513 Rd = 1 << 8;
1514 } else {
1515 Rd = 1 << 9;
1516 }
1517 break;
1518 case FP_ZERO:
1518 case FP_ZERO:
1519 if (signbit(fs1)) {
1520 Rd = 1 << 3;
1521 } else {
1522 Rd = 1 << 4;
1523 }
1524 break;
1519 if (signbit(fs1)) {
1520 Rd = 1 << 3;
1521 } else {
1522 Rd = 1 << 4;
1523 }
1524 break;
1525 case FP_SUBNORMAL:
1525 case FP_SUBNORMAL:
1526 if (signbit(fs1)) {
1527 Rd = 1 << 2;
1528 } else {
1529 Rd = 1 << 5;
1530 }
1531 break;
1526 if (signbit(fs1)) {
1527 Rd = 1 << 2;
1528 } else {
1529 Rd = 1 << 5;
1530 }
1531 break;
1532 case FP_NORMAL:
1532 case FP_NORMAL:
1533 if (signbit(fs1)) {
1534 Rd = 1 << 1;
1535 } else {
1536 Rd = 1 << 6;
1537 }
1538 break;
1533 if (signbit(fs1)) {
1534 Rd = 1 << 1;
1535 } else {
1536 Rd = 1 << 6;
1537 }
1538 break;
1539 default:
1539 default:
1540 panic("Unknown classification for operand.");
1541 break;
1542 }
1540 panic("Unknown classification for operand.");
1541 break;
1542 }
1543 }});
1543 }}, FloatMiscOp);
1544 }
1545 0x71: decode ROUND_MODE {
1546 0x0: fmv_x_d({{
1547 Rd = Fs1_bits;
1548 }}, FloatCvtOp);
1549 0x1: fclass_d({{
1550 switch (fpclassify(Fs1)) {
1544 }
1545 0x71: decode ROUND_MODE {
1546 0x0: fmv_x_d({{
1547 Rd = Fs1_bits;
1548 }}, FloatCvtOp);
1549 0x1: fclass_d({{
1550 switch (fpclassify(Fs1)) {
1551 case FP_INFINITE:
1551 case FP_INFINITE:
1552 if (signbit(Fs1)) {
1553 Rd = 1 << 0;
1554 } else {
1555 Rd = 1 << 7;
1556 }
1557 break;
1552 if (signbit(Fs1)) {
1553 Rd = 1 << 0;
1554 } else {
1555 Rd = 1 << 7;
1556 }
1557 break;
1558 case FP_NAN:
1558 case FP_NAN:
1559 if (issignalingnan(Fs1)) {
1560 Rd = 1 << 8;
1561 } else {
1562 Rd = 1 << 9;
1563 }
1564 break;
1559 if (issignalingnan(Fs1)) {
1560 Rd = 1 << 8;
1561 } else {
1562 Rd = 1 << 9;
1563 }
1564 break;
1565 case FP_ZERO:
1565 case FP_ZERO:
1566 if (signbit(Fs1)) {
1567 Rd = 1 << 3;
1568 } else {
1569 Rd = 1 << 4;
1570 }
1571 break;
1566 if (signbit(Fs1)) {
1567 Rd = 1 << 3;
1568 } else {
1569 Rd = 1 << 4;
1570 }
1571 break;
1572 case FP_SUBNORMAL:
1572 case FP_SUBNORMAL:
1573 if (signbit(Fs1)) {
1574 Rd = 1 << 2;
1575 } else {
1576 Rd = 1 << 5;
1577 }
1578 break;
1573 if (signbit(Fs1)) {
1574 Rd = 1 << 2;
1575 } else {
1576 Rd = 1 << 5;
1577 }
1578 break;
1579 case FP_NORMAL:
1579 case FP_NORMAL:
1580 if (signbit(Fs1)) {
1581 Rd = 1 << 1;
1582 } else {
1583 Rd = 1 << 6;
1584 }
1585 break;
1580 if (signbit(Fs1)) {
1581 Rd = 1 << 1;
1582 } else {
1583 Rd = 1 << 6;
1584 }
1585 break;
1586 default:
1586 default:
1587 panic("Unknown classification for operand.");
1588 break;
1589 }
1587 panic("Unknown classification for operand.");
1588 break;
1589 }
1590 }});
1590 }}, FloatMiscOp);
1591 }
1592 0x78: fmv_s_x({{
1593 Fd_bits = (uint64_t)Rs1_uw;
1594 }}, FloatCvtOp);
1595 0x79: fmv_d_x({{
1596 Fd_bits = Rs1;
1597 }}, FloatCvtOp);
1598 }

--- 113 unchanged lines hidden --- 		1591 }
1592 0x78: fmv_s_x({{
1593 Fd_bits = (uint64_t)Rs1_uw;
1594 }}, FloatCvtOp);
1595 0x79: fmv_d_x({{
1596 Fd_bits = Rs1;
1597 }}, FloatCvtOp);
1598 }

--- 113 unchanged lines hidden ---