decoder.isa (12322:e5a1d42b876b) decoder.isa (12428:ddc6b7179c81)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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31
32////////////////////////////////////////////////////////////////////
33//
34// The RISC-V ISA decoder
35//
36
37decode QUADRANT default Unknown::unknown() {
38 0x0: decode COPCODE {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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31
32////////////////////////////////////////////////////////////////////
33//
34// The RISC-V ISA decoder
35//
36
37decode QUADRANT default Unknown::unknown() {
38 0x0: decode COPCODE {
39 0x0: CUIOp::c_addi4spn({{
39 0x0: CIOp::c_addi4spn({{
40 imm = CIMM8<1:1> << 2 |
41 CIMM8<0:0> << 3 |
42 CIMM8<7:6> << 4 |
43 CIMM8<5:2> << 6;
44 }}, {{
45 if (machInst == 0)
46 fault = make_shared<IllegalInstFault>("zero instruction");
47 Rp2 = sp + imm;
40 imm = CIMM8<1:1> << 2 |
41 CIMM8<0:0> << 3 |
42 CIMM8<7:6> << 4 |
43 CIMM8<5:2> << 6;
44 }}, {{
45 if (machInst == 0)
46 fault = make_shared<IllegalInstFault>("zero instruction");
47 Rp2 = sp + imm;
48 }});
48 }}, uint64_t);
49 format CompressedLoad {
50 0x1: c_fld({{
51 offset = CIMM3 << 3 | CIMM2 << 6;
52 }}, {{
53 Fp2_bits = Mem;
54 }}, {{
55 EA = Rp1 + offset;
56 }});

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147 }}, {{
148 assert(RC1 != 0 && RC1 != 2);
149 assert(imm != 0);
150 Rc1_sd = imm;
151 }});
152 }
153 }
154 0x4: decode CFUNCT2HIGH {
49 format CompressedLoad {
50 0x1: c_fld({{
51 offset = CIMM3 << 3 | CIMM2 << 6;
52 }}, {{
53 Fp2_bits = Mem;
54 }}, {{
55 EA = Rp1 + offset;
56 }});

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147 }}, {{
148 assert(RC1 != 0 && RC1 != 2);
149 assert(imm != 0);
150 Rc1_sd = imm;
151 }});
152 }
153 }
154 0x4: decode CFUNCT2HIGH {
155 format CUIOp {
155 format CIOp {
156 0x0: c_srli({{
157 imm = CIMM5 | (CIMM1 << 5);
158 assert(imm != 0);
159 }}, {{
160 Rp1 = Rp1 >> imm;
156 0x0: c_srli({{
157 imm = CIMM5 | (CIMM1 << 5);
158 assert(imm != 0);
159 }}, {{
160 Rp1 = Rp1 >> imm;
161 }});
161 }}, uint64_t);
162 0x1: c_srai({{
163 imm = CIMM5 | (CIMM1 << 5);
164 assert(imm != 0);
165 }}, {{
166 Rp1_sd = Rp1_sd >> imm;
162 0x1: c_srai({{
163 imm = CIMM5 | (CIMM1 << 5);
164 assert(imm != 0);
165 }}, {{
166 Rp1_sd = Rp1_sd >> imm;
167 }});
167 }}, uint64_t);
168 0x2: c_andi({{
169 imm = CIMM5;
170 if (CIMM1 > 0)
171 imm |= ~((uint64_t)0x1F);
172 }}, {{
173 Rp1 = Rp1 & imm;
168 0x2: c_andi({{
169 imm = CIMM5;
170 if (CIMM1 > 0)
171 imm |= ~((uint64_t)0x1F);
172 }}, {{
173 Rp1 = Rp1 & imm;
174 }});
174 }}, uint64_t);
175 }
176 format ROp {
177 0x3: decode CFUNCT1 {
178 0x0: decode CFUNCT2LOW {
179 0x0: c_sub({{
180 Rp1 = Rp1 - Rp2;
181 }});
182 0x1: c_xor({{

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237 if (Rp1 != 0)
238 NPC = PC + offset;
239 else
240 NPC = NPC;
241 }}, IsDirectControl, IsCondControl);
242 }
243 }
244 0x2: decode COPCODE {
175 }
176 format ROp {
177 0x3: decode CFUNCT1 {
178 0x0: decode CFUNCT2LOW {
179 0x0: c_sub({{
180 Rp1 = Rp1 - Rp2;
181 }});
182 0x1: c_xor({{

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237 if (Rp1 != 0)
238 NPC = PC + offset;
239 else
240 NPC = NPC;
241 }}, IsDirectControl, IsCondControl);
242 }
243 }
244 0x2: decode COPCODE {
245 0x0: CUIOp::c_slli({{
245 0x0: CIOp::c_slli({{
246 imm = CIMM5 | (CIMM1 << 5);
247 assert(imm != 0);
248 }}, {{
249 assert(RC1 != 0);
250 Rc1 = Rc1 << imm;
246 imm = CIMM5 | (CIMM1 << 5);
247 assert(imm != 0);
248 }}, {{
249 assert(RC1 != 0);
250 Rc1 = Rc1 << imm;
251 }});
251 }}, uint64_t);
252 format CompressedLoad {
253 0x1: c_fldsp({{
254 offset = CIMM5<4:3> << 3 |
255 CIMM1 << 5 |
256 CIMM5<2:0> << 6;
257 }}, {{
258 Fc1_bits = Mem;
259 }}, {{

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371 Fd_bits = Mem;
372 }});
373 }
374 }
375
376 0x03: decode FUNCT3 {
377 format IOp {
378 0x0: fence({{
252 format CompressedLoad {
253 0x1: c_fldsp({{
254 offset = CIMM5<4:3> << 3 |
255 CIMM1 << 5 |
256 CIMM5<2:0> << 6;
257 }}, {{
258 Fc1_bits = Mem;
259 }}, {{

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371 Fd_bits = Mem;
372 }});
373 }
374 }
375
376 0x03: decode FUNCT3 {
377 format IOp {
378 0x0: fence({{
379 }}, IsNonSpeculative, IsMemBarrier, No_OpClass);
379 }}, uint64_t, IsNonSpeculative, IsMemBarrier, No_OpClass);
380 0x1: fence_i({{
380 0x1: fence_i({{
381 }}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
381 }}, uint64_t, IsNonSpeculative, IsSerializeAfter, No_OpClass);
382 }
383 }
384
385 0x04: decode FUNCT3 {
386 format IOp {
387 0x0: addi({{
388 Rd_sd = Rs1_sd + imm;
389 }});
390 0x1: slli({{
391 Rd = Rs1 << SHAMT6;
392 }});
393 0x2: slti({{
394 Rd = (Rs1_sd < imm) ? 1 : 0;
395 }});
396 0x3: sltiu({{
382 }
383 }
384
385 0x04: decode FUNCT3 {
386 format IOp {
387 0x0: addi({{
388 Rd_sd = Rs1_sd + imm;
389 }});
390 0x1: slli({{
391 Rd = Rs1 << SHAMT6;
392 }});
393 0x2: slti({{
394 Rd = (Rs1_sd < imm) ? 1 : 0;
395 }});
396 0x3: sltiu({{
397 Rd = (Rs1 < (uint64_t)imm) ? 1 : 0;
398 }});
397 Rd = (Rs1 < imm) ? 1 : 0;
398 }}, uint64_t);
399 0x4: xori({{
399 0x4: xori({{
400 Rd = Rs1 ^ (uint64_t)imm;
401 }});
400 Rd = Rs1 ^ imm;
401 }}, uint64_t);
402 0x5: decode SRTYPE {
403 0x0: srli({{
404 Rd = Rs1 >> SHAMT6;
405 }});
406 0x1: srai({{
407 Rd_sd = Rs1_sd >> SHAMT6;
408 }});
409 }
410 0x6: ori({{
402 0x5: decode SRTYPE {
403 0x0: srli({{
404 Rd = Rs1 >> SHAMT6;
405 }});
406 0x1: srai({{
407 Rd_sd = Rs1_sd >> SHAMT6;
408 }});
409 }
410 0x6: ori({{
411 Rd = Rs1 | (uint64_t)imm;
412 }});
411 Rd = Rs1 | imm;
412 }}, uint64_t);
413 0x7: andi({{
413 0x7: andi({{
414 Rd = Rs1 & (uint64_t)imm;
415 }});
414 Rd = Rs1 & imm;
415 }}, uint64_t);
416 }
417 }
418
419 0x05: UOp::auipc({{
420 Rd = PC + imm;
421 }});
422
423 0x06: decode FUNCT3 {
424 format IOp {
425 0x0: addiw({{
416 }
417 }
418
419 0x05: UOp::auipc({{
420 Rd = PC + imm;
421 }});
422
423 0x06: decode FUNCT3 {
424 format IOp {
425 0x0: addiw({{
426 Rd_sd = (int32_t)Rs1 + (int32_t)imm;
427 }});
426 Rd_sd = Rs1_sw + imm;
427 }}, int32_t);
428 0x1: slliw({{
429 Rd_sd = Rs1_sw << SHAMT5;
430 }});
431 0x5: decode SRTYPE {
432 0x0: srliw({{
433 Rd = Rs1_uw >> SHAMT5;
434 }});
435 0x1: sraiw({{

--- 1266 unchanged lines hidden --- 		428 0x1: slliw({{
429 Rd_sd = Rs1_sw << SHAMT5;
430 }});
431 0x5: decode SRTYPE {
432 0x0: srliw({{
433 Rd = Rs1_uw >> SHAMT5;
434 }});
435 0x1: sraiw({{

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