decoder.isa (12138:5f06b9aa2fde) decoder.isa (12322:e5a1d42b876b)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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43 CIMM8<5:2> << 6;
44 }}, {{
45 if (machInst == 0)
46 fault = make_shared<IllegalInstFault>("zero instruction");
47 Rp2 = sp + imm;
48 }});
49 format CompressedLoad {
50 0x1: c_fld({{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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43 CIMM8<5:2> << 6;
44 }}, {{
45 if (machInst == 0)
46 fault = make_shared<IllegalInstFault>("zero instruction");
47 Rp2 = sp + imm;
48 }});
49 format CompressedLoad {
50 0x1: c_fld({{
51 ldisp = CIMM3 << 3 | CIMM2 << 6;
51 offset = CIMM3 << 3 | CIMM2 << 6;
52 }}, {{
53 Fp2_bits = Mem;
54 }}, {{
52 }}, {{
53 Fp2_bits = Mem;
54 }}, {{
55 EA = Rp1 + ldisp;
55 EA = Rp1 + offset;
56 }});
57 0x2: c_lw({{
56 }});
57 0x2: c_lw({{
58 ldisp = CIMM2<1:1> << 2 |
59 CIMM3 << 3 |
60 CIMM2<0:0> << 6;
58 offset = CIMM2<1:1> << 2 |
59 CIMM3 << 3 |
60 CIMM2<0:0> << 6;
61 }}, {{
62 Rp2_sd = Mem_sw;
63 }}, {{
61 }}, {{
62 Rp2_sd = Mem_sw;
63 }}, {{
64 EA = Rp1 + ldisp;
64 EA = Rp1 + offset;
65 }});
66 0x3: c_ld({{
65 }});
66 0x3: c_ld({{
67 ldisp = CIMM3 << 3 | CIMM2 << 6;
67 offset = CIMM3 << 3 | CIMM2 << 6;
68 }}, {{
69 Rp2_sd = Mem_sd;
70 }}, {{
68 }}, {{
69 Rp2_sd = Mem_sd;
70 }}, {{
71 EA = Rp1 + ldisp;
71 EA = Rp1 + offset;
72 }});
73 }
74 format CompressedStore {
75 0x5: c_fsd({{
72 }});
73 }
74 format CompressedStore {
75 0x5: c_fsd({{
76 sdisp = CIMM3 << 3 | CIMM2 << 6;
76 offset = CIMM3 << 3 | CIMM2 << 6;
77 }}, {{
78 Mem = Fp2_bits;
79 }}, {{
77 }}, {{
78 Mem = Fp2_bits;
79 }}, {{
80 EA = Rp1 + sdisp;
80 EA = Rp1 + offset;
81 }});
82 0x6: c_sw({{
81 }});
82 0x6: c_sw({{
83 sdisp = CIMM2<1:1> << 2 |
84 CIMM3 << 3 |
85 CIMM2<0:0> << 6;
83 offset = CIMM2<1:1> << 2 |
84 CIMM3 << 3 |
85 CIMM2<0:0> << 6;
86 }}, {{
87 Mem_uw = Rp2_uw;
88 }}, ea_code={{
86 }}, {{
87 Mem_uw = Rp2_uw;
88 }}, ea_code={{
89 EA = Rp1 + sdisp;
89 EA = Rp1 + offset;
90 }});
91 0x7: c_sd({{
90 }});
91 0x7: c_sd({{
92 sdisp = CIMM3 << 3 | CIMM2 << 6;
92 offset = CIMM3 << 3 | CIMM2 << 6;
93 }}, {{
94 Mem_ud = Rp2_ud;
95 }}, {{
93 }}, {{
94 Mem_ud = Rp2_ud;
95 }}, {{
96 EA = Rp1 + sdisp;
96 EA = Rp1 + offset;
97 }});
98 }
99 }
100 0x1: decode COPCODE {
101 format CIOp {
102 0x0: c_addi({{
103 imm = CIMM5;
104 if (CIMM1 > 0)

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197 Rp1_sd = (int32_t)Rp1_sd + Rp2_sw;
198 }});
199 }
200 }
201 }
202 }
203 0x5: JOp::c_j({{
204 int64_t offset = CJUMPIMM<3:1> << 1 |
97 }});
98 }
99 }
100 0x1: decode COPCODE {
101 format CIOp {
102 0x0: c_addi({{
103 imm = CIMM5;
104 if (CIMM1 > 0)

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197 Rp1_sd = (int32_t)Rp1_sd + Rp2_sw;
198 }});
199 }
200 }
201 }
202 }
203 0x5: JOp::c_j({{
204 int64_t offset = CJUMPIMM<3:1> << 1 |
205 CJUMPIMM<9:9> << 4 |
206 CJUMPIMM<0:0> << 5 |
207 CJUMPIMM<5:5> << 6 |
208 CJUMPIMM<4:4> << 7 |
209 CJUMPIMM<8:7> << 8 |
210 CJUMPIMM<6:6> << 10;
205 CJUMPIMM<9:9> << 4 |
206 CJUMPIMM<0:0> << 5 |
207 CJUMPIMM<5:5> << 6 |
208 CJUMPIMM<4:4> << 7 |
209 CJUMPIMM<8:7> << 8 |
210 CJUMPIMM<6:6> << 10;
211 if (CJUMPIMM<10:10> > 0)
212 offset |= ~((int64_t)0x7FF);
213 NPC = PC + offset;
214 }}, IsIndirectControl, IsUncondControl, IsCall);
215 format BOp {
216 0x6: c_beqz({{
217 int64_t offset = CIMM5<2:1> << 1 |
218 CIMM3<1:0> << 3 |

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246 imm = CIMM5 | (CIMM1 << 5);
247 assert(imm != 0);
248 }}, {{
249 assert(RC1 != 0);
250 Rc1 = Rc1 << imm;
251 }});
252 format CompressedLoad {
253 0x1: c_fldsp({{
211 if (CJUMPIMM<10:10> > 0)
212 offset |= ~((int64_t)0x7FF);
213 NPC = PC + offset;
214 }}, IsIndirectControl, IsUncondControl, IsCall);
215 format BOp {
216 0x6: c_beqz({{
217 int64_t offset = CIMM5<2:1> << 1 |
218 CIMM3<1:0> << 3 |

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246 imm = CIMM5 | (CIMM1 << 5);
247 assert(imm != 0);
248 }}, {{
249 assert(RC1 != 0);
250 Rc1 = Rc1 << imm;
251 }});
252 format CompressedLoad {
253 0x1: c_fldsp({{
254 ldisp = CIMM5<4:3> << 3 |
255 CIMM1 << 5 |
256 CIMM5<2:0> << 6;
254 offset = CIMM5<4:3> << 3 |
255 CIMM1 << 5 |
256 CIMM5<2:0> << 6;
257 }}, {{
258 Fc1_bits = Mem;
259 }}, {{
257 }}, {{
258 Fc1_bits = Mem;
259 }}, {{
260 EA = sp + ldisp;
260 EA = sp + offset;
261 }});
262 0x2: c_lwsp({{
261 }});
262 0x2: c_lwsp({{
263 ldisp = CIMM5<4:2> << 2 |
264 CIMM1 << 5 |
265 CIMM5<1:0> << 6;
263 offset = CIMM5<4:2> << 2 |
264 CIMM1 << 5 |
265 CIMM5<1:0> << 6;
266 }}, {{
267 assert(RC1 != 0);
268 Rc1_sd = Mem_sw;
269 }}, {{
266 }}, {{
267 assert(RC1 != 0);
268 Rc1_sd = Mem_sw;
269 }}, {{
270 EA = sp + ldisp;
270 EA = sp + offset;
271 }});
272 0x3: c_ldsp({{
271 }});
272 0x3: c_ldsp({{
273 ldisp = CIMM5<4:3> << 3 |
274 CIMM1 << 5 |
275 CIMM5<2:0> << 6;
273 offset = CIMM5<4:3> << 3 |
274 CIMM1 << 5 |
275 CIMM5<2:0> << 6;
276 }}, {{
277 assert(RC1 != 0);
278 Rc1_sd = Mem_sd;
279 }}, {{
276 }}, {{
277 assert(RC1 != 0);
278 Rc1_sd = Mem_sd;
279 }}, {{
280 EA = sp + ldisp;
280 EA = sp + offset;
281 }});
282 }
283 0x4: decode CFUNCT1 {
284 0x0: decode RC2 {
285 0x0: Jump::c_jr({{
286 assert(RC1 != 0);
287 NPC = Rc1;
288 }}, IsIndirectControl, IsUncondControl, IsCall);

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305 default: ROp::c_add({{
306 Rc1_sd = Rc1_sd + Rc2_sd;
307 }});
308 }
309 }
310 }
311 format CompressedStore {
312 0x5: c_fsdsp({{
281 }});
282 }
283 0x4: decode CFUNCT1 {
284 0x0: decode RC2 {
285 0x0: Jump::c_jr({{
286 assert(RC1 != 0);
287 NPC = Rc1;
288 }}, IsIndirectControl, IsUncondControl, IsCall);

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305 default: ROp::c_add({{
306 Rc1_sd = Rc1_sd + Rc2_sd;
307 }});
308 }
309 }
310 }
311 format CompressedStore {
312 0x5: c_fsdsp({{
313 sdisp = CIMM6<5:3> << 3 |
314 CIMM6<2:0> << 6;
313 offset = CIMM6<5:3> << 3 |
314 CIMM6<2:0> << 6;
315 }}, {{
316 Mem_ud = Fc2_bits;
317 }}, {{
315 }}, {{
316 Mem_ud = Fc2_bits;
317 }}, {{
318 EA = sp + sdisp;
318 EA = sp + offset;
319 }});
320 0x6: c_swsp({{
319 }});
320 0x6: c_swsp({{
321 sdisp = CIMM6<5:2> << 2 |
322 CIMM6<1:0> << 6;
321 offset = CIMM6<5:2> << 2 |
322 CIMM6<1:0> << 6;
323 }}, {{
324 Mem_uw = Rc2_uw;
325 }}, {{
323 }}, {{
324 Mem_uw = Rc2_uw;
325 }}, {{
326 EA = sp + sdisp;
326 EA = sp + offset;
327 }});
328 0x7: c_sdsp({{
327 }});
328 0x7: c_sdsp({{
329 sdisp = CIMM6<5:3> << 3 |
330 CIMM6<2:0> << 6;
329 offset = CIMM6<5:3> << 3 |
330 CIMM6<2:0> << 6;
331 }}, {{
332 Mem = Rc2;
333 }}, {{
331 }}, {{
332 Mem = Rc2;
333 }}, {{
334 EA = sp + sdisp;
334 EA = sp + offset;
335 }});
336 }
337 }
338 0x3: decode OPCODE {
339 0x00: decode FUNCT3 {
340 format Load {
341 0x0: lb({{
342 Rd_sd = Mem_sb;

--- 1359 unchanged lines hidden --- 		335 }});
336 }
337 }
338 0x3: decode OPCODE {
339 0x00: decode FUNCT3 {
340 format Load {
341 0x0: lb({{
342 Rd_sd = Mem_sb;

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