decoder.isa (11726:11950d45640b) decoder.isa (11729:f37b5fcd66fe)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

--- 204 unchanged lines hidden (view full) ---

213 Mem_sw = std::max<uint32_t>(Rs2_uw, Rt_sd);
214 Rd_sd = Rt_sd;
215 }}, {{EA = Rs1;}});
216 }
217 }
218 0x3: decode AMOFUNCT {
219 0x2: LoadReserved::lr_d({{
220 Rd_sd = Mem_sd;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

--- 204 unchanged lines hidden (view full) ---

213 Mem_sw = std::max<uint32_t>(Rs2_uw, Rt_sd);
214 Rd_sd = Rt_sd;
215 }}, {{EA = Rs1;}});
216 }
217 }
218 0x3: decode AMOFUNCT {
219 0x2: LoadReserved::lr_d({{
220 Rd_sd = Mem_sd;
221 }}, aq=AQ, rl=RL);
221 }}, mem_flags=LLSC, aq=AQ, rl=RL);
222 0x3: StoreCond::sc_d({{
223 Mem = Rs2;
224 }}, {{
225 Rd = result;
222 0x3: StoreCond::sc_d({{
223 Mem = Rs2;
224 }}, {{
225 Rd = result;
226 }}, aq=AQ, rl=RL);
226 }}, mem_flags=LLSC, inst_flags=IsStoreConditional, aq=AQ, rl=RL);
227 format AtomicMemOp {
228 0x0: amoadd_d({{Rt_sd = Mem_sd;}}, {{
229 Mem_sd = Rs2_sd + Rt_sd;
230 Rd_sd = Rt_sd;
231 }}, {{EA = Rs1;}});
232 0x1: amoswap_d({{Rt = Mem;}}, {{
233 Mem = Rs2;
234 Rd = Rt;

--- 1149 unchanged lines hidden --- 		227 format AtomicMemOp {
228 0x0: amoadd_d({{Rt_sd = Mem_sd;}}, {{
229 Mem_sd = Rs2_sd + Rt_sd;
230 Rd_sd = Rt_sd;
231 }}, {{EA = Rs1;}});
232 0x1: amoswap_d({{Rt = Mem;}}, {{
233 Mem = Rs2;
234 Rd = Rt;

--- 1149 unchanged lines hidden ---