1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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1703 Rd = NPC;
1704 NPC = PC + imm;
1705 }}, IsDirectControl, IsUncondControl, IsCall);
1706
1707 0x1c: decode FUNCT3 {
1708 format SystemOp {
1709 0x0: decode FUNCT12 {
1710 0x0: ecall({{
1711 fault = make_shared<SyscallFault>();
1712 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall,
1713 No_OpClass);
1714 0x1: ebreak({{
1715 fault = make_shared<BreakpointFault>(xc->pcState());
1716 }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
1717 0x100: eret({{
1718 fault = make_shared<UnimplementedFault>("eret",
1719 machInst);
1720 }}, No_OpClass);
1721 }
1722 }
1723 format CSROp {
1724 0x1: csrrw({{
1725 Rd = data;
1726 data = Rs1;
1727 }}, IsNonSpeculative, No_OpClass);
1728 0x2: csrrs({{

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