1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

--- 770 unchanged lines hidden (view full) ---

779 0x10: decode FUNCT2 {
780 0x0: fmadd_s({{
781 uint32_t temp;
782 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
783 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
784 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
785 float fd;
786
787 if (isnan(fs1) || isnan(fs2) || isnan(fs3)) {
788 if (issignalingnan(fs1) || issignalingnan(fs2)
789 || issignalingnan(fs3)) {
790 FFLAGS |= FloatInvalid;
791 }
792 fd = numeric_limits<float>::quiet_NaN();
793 } else if (isinf(fs1) || isinf(fs2) ||
794 isinf(fs3)) {
795 if (signbit(fs1) == signbit(fs2)
796 && !isinf(fs3)) {
797 fd = numeric_limits<float>::infinity();
798 } else if (signbit(fs1) != signbit(fs2)
799 && !isinf(fs3)) {
800 fd = -numeric_limits<float>::infinity();
801 } else { // Fs3_sf is infinity
802 fd = fs3;
803 }
804 } else {
805 fd = fs1*fs2 + fs3;
806 }
807 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
808 }}, FloatMultOp);
809 0x1: fmadd_d({{
810 if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) {
811 if (issignalingnan(Fs1) || issignalingnan(Fs2)
812 || issignalingnan(Fs3)) {
813 FFLAGS |= FloatInvalid;
814 }
815 Fd = numeric_limits<double>::quiet_NaN();
816 } else if (isinf(Fs1) || isinf(Fs2) ||
817 isinf(Fs3)) {
818 if (signbit(Fs1) == signbit(Fs2)
819 && !isinf(Fs3)) {
820 Fd = numeric_limits<double>::infinity();
821 } else if (signbit(Fs1) != signbit(Fs2)
822 && !isinf(Fs3)) {
823 Fd = -numeric_limits<double>::infinity();
824 } else {
825 Fd = Fs3;
826 }
827 } else {
828 Fd = Fs1*Fs2 + Fs3;
829 }
830 }}, FloatMultOp);
831 }
832 0x11: decode FUNCT2 {
833 0x0: fmsub_s({{
834 uint32_t temp;
835 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
836 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
837 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
838 float fd;
839
840 if (isnan(fs1) || isnan(fs2) || isnan(fs3)) {
841 if (issignalingnan(fs1) || issignalingnan(fs2)
842 || issignalingnan(fs3)) {
843 FFLAGS |= FloatInvalid;
844 }
845 fd = numeric_limits<float>::quiet_NaN();
846 } else if (isinf(fs1) || isinf(fs2) ||
847 isinf(fs3)) {
848 if (signbit(fs1) == signbit(fs2)
849 && !isinf(fs3)) {
850 fd = numeric_limits<float>::infinity();
851 } else if (signbit(fs1) != signbit(fs2)
852 && !isinf(fs3)) {
853 fd = -numeric_limits<float>::infinity();
854 } else { // Fs3_sf is infinity
855 fd = -fs3;
856 }
857 } else {
858 fd = fs1*fs2 - fs3;
859 }
860 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
861 }}, FloatMultOp);
862 0x1: fmsub_d({{
863 if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) {
864 if (issignalingnan(Fs1) || issignalingnan(Fs2)
865 || issignalingnan(Fs3)) {
866 FFLAGS |= FloatInvalid;
867 }
868 Fd = numeric_limits<double>::quiet_NaN();
869 } else if (isinf(Fs1) || isinf(Fs2) ||
870 isinf(Fs3)) {
871 if (signbit(Fs1) == signbit(Fs2)
872 && !isinf(Fs3)) {
873 Fd = numeric_limits<double>::infinity();
874 } else if (signbit(Fs1) != signbit(Fs2)
875 && !isinf(Fs3)) {
876 Fd = -numeric_limits<double>::infinity();
877 } else {
878 Fd = -Fs3;
879 }
880 } else {
881 Fd = Fs1*Fs2 - Fs3;
882 }
883 }}, FloatMultOp);
884 }
885 0x12: decode FUNCT2 {
886 0x0: fnmsub_s({{
887 uint32_t temp;
888 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
889 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
890 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
891 float fd;
892
893 if (isnan(fs1) || isnan(fs2) || isnan(fs3)) {
894 if (issignalingnan(fs1) || issignalingnan(fs2)
895 || issignalingnan(fs3)) {
896 FFLAGS |= FloatInvalid;
897 }
898 fd = numeric_limits<float>::quiet_NaN();
899 } else if (isinf(fs1) || isinf(fs2) ||
900 isinf(fs3)) {
901 if (signbit(fs1) == signbit(fs2)
902 && !isinf(fs3)) {
903 fd = -numeric_limits<float>::infinity();
904 } else if (signbit(fs1) != signbit(fs2)
905 && !isinf(fs3)) {
906 fd = numeric_limits<float>::infinity();
907 } else { // Fs3_sf is infinity
908 fd = fs3;
909 }
910 } else {
911 fd = -(fs1*fs2 - fs3);
912 }
913 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
914 }}, FloatMultOp);
915 0x1: fnmsub_d({{
916 if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) {
917 if (issignalingnan(Fs1) || issignalingnan(Fs2)
918 || issignalingnan(Fs3)) {
919 FFLAGS |= FloatInvalid;
920 }
921 Fd = numeric_limits<double>::quiet_NaN();
922 } else if (isinf(Fs1) || isinf(Fs2)
923 || isinf(Fs3)) {
924 if (signbit(Fs1) == signbit(Fs2)
925 && !isinf(Fs3)) {
926 Fd = -numeric_limits<double>::infinity();
927 } else if (signbit(Fs1) != signbit(Fs2)
928 && !isinf(Fs3)) {
929 Fd = numeric_limits<double>::infinity();
930 } else {
931 Fd = Fs3;
932 }
933 } else {
934 Fd = -(Fs1*Fs2 - Fs3);
935 }
936 }}, FloatMultOp);
937 }
938 0x13: decode FUNCT2 {
939 0x0: fnmadd_s({{
940 uint32_t temp;
941 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
942 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
943 float fs3 = reinterpret_cast<float&>(temp = Fs3_bits);
944 float fd;
945
946 if (isnan(fs1) || isnan(fs2) || isnan(fs3)) {
947 if (issignalingnan(fs1) || issignalingnan(fs2)
948 || issignalingnan(fs3)) {
949 FFLAGS |= FloatInvalid;
950 }
951 fd = numeric_limits<float>::quiet_NaN();
952 } else if (isinf(fs1) || isinf(fs2) ||
953 isinf(fs3)) {
954 if (signbit(fs1) == signbit(fs2)
955 && !isinf(fs3)) {
956 fd = -numeric_limits<float>::infinity();
957 } else if (signbit(fs1) != signbit(fs2)
958 && !isinf(fs3)) {
959 fd = numeric_limits<float>::infinity();
960 } else { // Fs3_sf is infinity
961 fd = -fs3;
962 }
963 } else {
964 fd = -(fs1*fs2 + fs3);
965 }
966 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
967 }}, FloatMultOp);
968 0x1: fnmadd_d({{
969 if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) {
970 if (issignalingnan(Fs1) || issignalingnan(Fs2)
971 || issignalingnan(Fs3)) {
972 FFLAGS |= FloatInvalid;
973 }
974 Fd = numeric_limits<double>::quiet_NaN();
975 } else if (isinf(Fs1) || isinf(Fs2) ||
976 isinf(Fs3)) {
977 if (signbit(Fs1) == signbit(Fs2)
978 && !isinf(Fs3)) {
979 Fd = -numeric_limits<double>::infinity();
980 } else if (signbit(Fs1) != signbit(Fs2)
981 && !isinf(Fs3)) {
982 Fd = numeric_limits<double>::infinity();
983 } else {
984 Fd = -Fs3;
985 }
986 } else {
987 Fd = -(Fs1*Fs2 + Fs3);
988 }
989 }}, FloatMultOp);
990 }
991 0x14: decode FUNCT7 {
992 0x0: fadd_s({{
993 uint32_t temp;
994 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
995 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
996 float fd;
997
998 if (isnan(fs1) || isnan(fs2)) {
999 if (issignalingnan(fs1) || issignalingnan(fs2)) {
1000 FFLAGS |= FloatInvalid;
1001 }
1002 fd = numeric_limits<float>::quiet_NaN();
1003 } else {
1004 fd = fs1 + fs2;
1005 }
1006 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1007 }}, FloatAddOp);
1008 0x1: fadd_d({{
1009 if (isnan(Fs1) || isnan(Fs2)) {
1010 if (issignalingnan(Fs1) || issignalingnan(Fs2)) {
1011 FFLAGS |= FloatInvalid;
1012 }
1013 Fd = numeric_limits<double>::quiet_NaN();
1014 } else {
1015 Fd = Fs1 + Fs2;
1016 }
1017 }}, FloatAddOp);
1018 0x4: fsub_s({{
1019 uint32_t temp;
1020 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1021 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1022 float fd;
1023
1024 if (isnan(fs1) || isnan(fs2)) {
1025 if (issignalingnan(fs1) || issignalingnan(fs2)) {
1026 FFLAGS |= FloatInvalid;
1027 }
1028 fd = numeric_limits<float>::quiet_NaN();
1029 } else {
1030 fd = fs1 - fs2;
1031 }
1032 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1033 }}, FloatAddOp);
1034 0x5: fsub_d({{
1035 if (isnan(Fs1) || isnan(Fs2)) {
1036 if (issignalingnan(Fs1) || issignalingnan(Fs2)) {
1037 FFLAGS |= FloatInvalid;
1038 }
1039 Fd = numeric_limits<double>::quiet_NaN();
1040 } else {
1041 Fd = Fs1 - Fs2;
1042 }
1043 }}, FloatAddOp);
1044 0x8: fmul_s({{
1045 uint32_t temp;
1046 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1047 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1048 float fd;
1049
1050 if (isnan(fs1) || isnan(fs2)) {
1051 if (issignalingnan(fs1) || issignalingnan(fs2)) {
1052 FFLAGS |= FloatInvalid;
1053 }
1054 fd = numeric_limits<float>::quiet_NaN();
1055 } else {
1056 fd = fs1*fs2;
1057 }
1058 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1059 }}, FloatMultOp);
1060 0x9: fmul_d({{
1061 if (isnan(Fs1) || isnan(Fs2)) {
1062 if (issignalingnan(Fs1) || issignalingnan(Fs2)) {
1063 FFLAGS |= FloatInvalid;
1064 }
1065 Fd = numeric_limits<double>::quiet_NaN();
1066 } else {
1067 Fd = Fs1*Fs2;
1068 }
1069 }}, FloatMultOp);
1070 0xc: fdiv_s({{
1071 uint32_t temp;
1072 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1073 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1074 float fd;
1075
1076 if (isnan(fs1) || isnan(fs2)) {
1077 if (issignalingnan(fs1) || issignalingnan(fs2)) {
1078 FFLAGS |= FloatInvalid;
1079 }
1080 fd = numeric_limits<float>::quiet_NaN();
1081 } else {
1082 fd = fs1/fs2;
1083 }
1084 Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd);
1085 }}, FloatDivOp);
1086 0xd: fdiv_d({{
1087 if (isnan(Fs1) || isnan(Fs2)) {
1088 if (issignalingnan(Fs1) || issignalingnan(Fs2)) {
1089 FFLAGS |= FloatInvalid;
1090 }
1091 Fd = numeric_limits<double>::quiet_NaN();
1092 } else {
1093 Fd = Fs1/Fs2;
1094 }
1095 }}, FloatDivOp);

--- 167 unchanged lines hidden (view full) ---

1263 Fd = sqrt(Fs1);
1264 }}, FloatSqrtOp);
1265 0x50: decode ROUND_MODE {
1266 0x0: fle_s({{
1267 uint32_t temp;
1268 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1269 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1270
1271 if (isnan(fs1) || isnan(fs2)) {
1272 FFLAGS |= FloatInvalid;
1273 Rd = 0;
1274 } else {
1275 Rd = fs1 <= fs2 ? 1 : 0;
1276 }
1277 }}, FloatCmpOp);
1278 0x1: flt_s({{
1279 uint32_t temp;
1280 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1281 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1282
1283 if (isnan(fs1) || isnan(fs2)) {
1284 FFLAGS |= FloatInvalid;
1285 Rd = 0;
1286 } else {
1287 Rd = fs1 < fs2 ? 1 : 0;
1288 }
1289 }}, FloatCmpOp);
1290 0x2: feq_s({{
1291 uint32_t temp;
1292 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1293 float fs2 = reinterpret_cast<float&>(temp = Fs2_bits);
1294
1295 if (issignalingnan(fs1) || issignalingnan(fs2)) {
1296 FFLAGS |= FloatInvalid;
1297 }
1298 Rd = fs1 == fs2 ? 1 : 0;
1299 }}, FloatCmpOp);
1300 }
1301 0x51: decode ROUND_MODE {
1302 0x0: fle_d({{
1303 if (isnan(Fs1) || isnan(Fs2)) {
1304 FFLAGS |= FloatInvalid;
1305 Rd = 0;
1306 } else {
1307 Rd = Fs1 <= Fs2 ? 1 : 0;
1308 }
1309 }}, FloatCmpOp);
1310 0x1: flt_d({{
1311 if (isnan(Fs1) || isnan(Fs2)) {
1312 FFLAGS |= FloatInvalid;
1313 Rd = 0;
1314 } else {
1315 Rd = Fs1 < Fs2 ? 1 : 0;
1316 }
1317 }}, FloatCmpOp);
1318 0x2: feq_d({{
1319 if (issignalingnan(Fs1) || issignalingnan(Fs2)) {
1320 FFLAGS |= FloatInvalid;
1321 }
1322 Rd = Fs1 == Fs2 ? 1 : 0;
1323 }}, FloatCmpOp);
1324 }
1325 0x60: decode CONV_SGN {
1326 0x0: fcvt_w_s({{
1327 uint32_t temp;
1328 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1329
1330 if (isnan(fs1)) {
1331 Rd_sd = numeric_limits<int32_t>::max();
1332 FFLAGS |= FloatInvalid;
1333 } else {
1334 Rd_sd = (int32_t)fs1;
1335 if (fetestexcept(FE_INVALID)) {
1336 if (signbit(fs1)) {
1337 Rd_sd = numeric_limits<int32_t>::min();
1338 } else {

--- 17 unchanged lines hidden (view full) ---

1356 feclearexcept(FE_INEXACT);
1357 }
1358 }
1359 }}, FloatCvtOp);
1360 0x2: fcvt_l_s({{
1361 uint32_t temp;
1362 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
1363
1364 if (isnan(fs1)) {
1365 Rd_sd = numeric_limits<int64_t>::max();
1366 FFLAGS |= FloatInvalid;
1367 } else {
1368 Rd_sd = (int64_t)fs1;
1369 if (fetestexcept(FE_INVALID)) {
1370 if (signbit(fs1)) {
1371 Rd_sd = numeric_limits<int64_t>::min();
1372 } else {

--- 321 unchanged lines hidden ---