tlb.cc (8607:5fb918115c07) tlb.cc (8772:a5a83fc04972)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without

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45#include "base/inifile.hh"
46#include "base/str.hh"
47#include "base/trace.hh"
48#include "cpu/thread_context.hh"
49#include "debug/Power.hh"
50#include "debug/TLB.hh"
51#include "mem/page_table.hh"
52#include "params/PowerTLB.hh"
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without

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45#include "base/inifile.hh"
46#include "base/str.hh"
47#include "base/trace.hh"
48#include "cpu/thread_context.hh"
49#include "debug/Power.hh"
50#include "debug/TLB.hh"
51#include "mem/page_table.hh"
52#include "params/PowerTLB.hh"
53#include "sim/full_system.hh"
53#include "sim/process.hh"
54
55using namespace std;
56using namespace PowerISA;
57
58///////////////////////////////////////////////////////////////////////
59//
60// POWER TLB

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113 assert(Index<size);
114 return &table[Index];
115}
116
117int
118TLB::probeEntry(Addr vpn,uint8_t asn) const
119{
120 // assume not found...
54#include "sim/process.hh"
55
56using namespace std;
57using namespace PowerISA;
58
59///////////////////////////////////////////////////////////////////////
60//
61// POWER TLB

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114 assert(Index<size);
115 return &table[Index];
116}
117
118int
119TLB::probeEntry(Addr vpn,uint8_t asn) const
120{
121 // assume not found...
122 PowerISA::PTE *retval = NULL;
121 int Ind = -1;
122 PageTable::const_iterator i = lookupTable.find(vpn);
123 if (i != lookupTable.end()) {
124 while (i->first == vpn) {
125 int index = i->second;
126 PowerISA::PTE *pte = &table[index];
127 Addr Mask = pte->Mask;
128 Addr InvMask = ~Mask;
129 Addr VPN = pte->VPN;
130 if (((vpn & InvMask) == (VPN & InvMask))
131 && (pte->G || (asn == pte->asid))) {
132
133 // We have a VPN + ASID Match
123 int Ind = -1;
124 PageTable::const_iterator i = lookupTable.find(vpn);
125 if (i != lookupTable.end()) {
126 while (i->first == vpn) {
127 int index = i->second;
128 PowerISA::PTE *pte = &table[index];
129 Addr Mask = pte->Mask;
130 Addr InvMask = ~Mask;
131 Addr VPN = pte->VPN;
132 if (((vpn & InvMask) == (VPN & InvMask))
133 && (pte->G || (asn == pte->asid))) {
134
135 // We have a VPN + ASID Match
136 retval = pte;
134 Ind = index;
135 break;
136 }
137 ++i;
138 }
139 }
140
141 DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind);

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303 return fault;
304
305 return NoFault;
306}
307
308Fault
309TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
310{
137 Ind = index;
138 break;
139 }
140 ++i;
141 }
142 }
143
144 DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind);

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306 return fault;
307
308 return NoFault;
309}
310
311Fault
312TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
313{
311#if !FULL_SYSTEM
312 if (mode == Execute)
313 return translateInst(req, tc);
314 else
315 return translateData(req, tc, mode == Write);
316#else
317 fatal("translate atomic not yet implemented\n");
318#endif
314 if (FullSystem) {
315 fatal("translate atomic not yet implemented in full system mode.\n");
316 } else {
317 if (mode == Execute)
318 return translateInst(req, tc);
319 else
320 return translateData(req, tc, mode == Write);
321 }
319}
320
321void
322TLB::translateTiming(RequestPtr req, ThreadContext *tc,
323 Translation *translation, Mode mode)
324{
325 assert(translation);
326 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);

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323
324void
325TLB::translateTiming(RequestPtr req, ThreadContext *tc,
326 Translation *translation, Mode mode)
327{
328 assert(translation);
329 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);

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