tlb.cc (12406:86bde4a026b5) tlb.cc (12749:223c83ed9979)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without

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140 }
141 }
142
143 DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind);
144 return Ind;
145}
146
147inline Fault
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without

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140 }
141 }
142
143 DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind);
144 return Ind;
145}
146
147inline Fault
148TLB::checkCacheability(RequestPtr &req)
148TLB::checkCacheability(const RequestPtr &req)
149{
150 Addr VAddrUncacheable = 0xA0000000;
151 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
152
153 // mark request as uncacheable
154 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
155 }
156 return NoFault;

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274 ;
275
276 hits = read_hits + write_hits;
277 misses = read_misses + write_misses;
278 accesses = read_accesses + write_accesses;
279}
280
281Fault
149{
150 Addr VAddrUncacheable = 0xA0000000;
151 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
152
153 // mark request as uncacheable
154 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
155 }
156 return NoFault;

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274 ;
275
276 hits = read_hits + write_hits;
277 misses = read_misses + write_misses;
278 accesses = read_accesses + write_accesses;
279}
280
281Fault
282TLB::translateInst(RequestPtr req, ThreadContext *tc)
282TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
283{
284 // Instruction accesses must be word-aligned
285 if (req->getVaddr() & 0x3) {
286 DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
287 req->getSize());
288 return std::make_shared<AlignmentFault>();
289 }
290
291 Process * p = tc->getProcessPtr();
292
293 Fault fault = p->pTable->translate(req);
294 if (fault != NoFault)
295 return fault;
296
297 return NoFault;
298}
299
300Fault
283{
284 // Instruction accesses must be word-aligned
285 if (req->getVaddr() & 0x3) {
286 DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
287 req->getSize());
288 return std::make_shared<AlignmentFault>();
289 }
290
291 Process * p = tc->getProcessPtr();
292
293 Fault fault = p->pTable->translate(req);
294 if (fault != NoFault)
295 return fault;
296
297 return NoFault;
298}
299
300Fault
301TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
301TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
302{
303 Process * p = tc->getProcessPtr();
304
305 Fault fault = p->pTable->translate(req);
306 if (fault != NoFault)
307 return fault;
308
309 return NoFault;
310}
311
312Fault
302{
303 Process * p = tc->getProcessPtr();
304
305 Fault fault = p->pTable->translate(req);
306 if (fault != NoFault)
307 return fault;
308
309 return NoFault;
310}
311
312Fault
313TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
313TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
314{
315 if (FullSystem)
316 fatal("translate atomic not yet implemented in full system mode.\n");
317
318 if (mode == Execute)
319 return translateInst(req, tc);
320 else
321 return translateData(req, tc, mode == Write);
322}
323
324void
314{
315 if (FullSystem)
316 fatal("translate atomic not yet implemented in full system mode.\n");
317
318 if (mode == Execute)
319 return translateInst(req, tc);
320 else
321 return translateData(req, tc, mode == Write);
322}
323
324void
325TLB::translateTiming(RequestPtr req, ThreadContext *tc,
325TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
326 Translation *translation, Mode mode)
327{
328 assert(translation);
329 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
330}
331
332Fault
326 Translation *translation, Mode mode)
327{
328 assert(translation);
329 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
330}
331
332Fault
333TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
333TLB::finalizePhysical(const RequestPtr &req,
334 ThreadContext *tc, Mode mode) const
334{
335 return NoFault;
336}
337
338PowerISA::PTE &
339TLB::index(bool advance)
340{
341 PowerISA::PTE *pte = &table[nlu];

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336 return NoFault;
337}
338
339PowerISA::PTE &
340TLB::index(bool advance)
341{
342 PowerISA::PTE *pte = &table[nlu];

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