1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution;
15 * neither the name of the copyright holders nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Authors: Nathan Binkert
32 * Steve Reinhardt
33 * Jaidev Patwardhan
34 * Stephen Hines
35 * Timothy M. Jones
36 */
37
38#include <string>
39#include <vector>
40
41#include "arch/power/faults.hh"
42#include "arch/power/pagetable.hh"
43#include "arch/power/tlb.hh"
44#include "arch/power/utility.hh"
45#include "base/inifile.hh"
46#include "base/str.hh"
47#include "base/trace.hh"
48#include "cpu/thread_context.hh"
49#include "debug/Power.hh"
50#include "debug/TLB.hh"
51#include "mem/page_table.hh"
52#include "params/PowerTLB.hh"
53#include "sim/process.hh"
54
55using namespace std;
56using namespace PowerISA;
57
58///////////////////////////////////////////////////////////////////////
59//
60// POWER TLB
61//
62
63#define MODE2MASK(X) (1 << (X))
64
65TLB::TLB(const Params *p)
66 : BaseTLB(p), size(p->size), nlu(0)
67{
68 table = new PowerISA::PTE[size];
69 memset(table, 0, sizeof(PowerISA::PTE[size]));
70 smallPages = 0;
71}
72
73TLB::~TLB()
74{
75 if (table)
76 delete [] table;
77}
78
79// look up an entry in the TLB
80PowerISA::PTE *
81TLB::lookup(Addr vpn, uint8_t asn) const
82{
83 // assume not found...
84 PowerISA::PTE *retval = NULL;
85 PageTable::const_iterator i = lookupTable.find(vpn);
86 if (i != lookupTable.end()) {
87 while (i->first == vpn) {
88 int index = i->second;
89 PowerISA::PTE *pte = &table[index];
90 Addr Mask = pte->Mask;
91 Addr InvMask = ~Mask;
92 Addr VPN = pte->VPN;
93 if (((vpn & InvMask) == (VPN & InvMask))
94 && (pte->G || (asn == pte->asid))) {
95
96 // We have a VPN + ASID Match
97 retval = pte;
98 break;
99 }
100 ++i;
101 }
102 }
103
104 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
105 retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
106 return retval;
107}
108
109PowerISA::PTE*
110TLB::getEntry(unsigned Index) const
111{
112 // Make sure that Index is valid
113 assert(Index<size);
114 return &table[Index];
115}
116
117int
118TLB::probeEntry(Addr vpn,uint8_t asn) const
119{
120 // assume not found...
121 PowerISA::PTE *retval = NULL;
122 int Ind = -1;
123 PageTable::const_iterator i = lookupTable.find(vpn);
124 if (i != lookupTable.end()) {
125 while (i->first == vpn) {
126 int index = i->second;
127 PowerISA::PTE *pte = &table[index];
128 Addr Mask = pte->Mask;
129 Addr InvMask = ~Mask;
130 Addr VPN = pte->VPN;
131 if (((vpn & InvMask) == (VPN & InvMask))
132 && (pte->G || (asn == pte->asid))) {
133
134 // We have a VPN + ASID Match
135 retval = pte;
136 Ind = index;
137 break;
138 }
139 ++i;
140 }
141 }
142
143 DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind);
144 return Ind;
145}
146
147inline Fault
148TLB::checkCacheability(RequestPtr &req)
149{
150 Addr VAddrUncacheable = 0xA0000000;
151 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
152
153 // mark request as uncacheable
154 req->setFlags(Request::UNCACHEABLE);
155 }
156 return NoFault;
157}
158
159void
160TLB::insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages)
161{
162 smallPages=_smallPages;
163 if (Index > size){
164 warn("Attempted to write at index (%d) beyond TLB size (%d)",
165 Index, size);
166 } else {
167
168 // Update TLB
169 if (table[Index].V0 == true || table[Index].V1 == true) {
170
171 // Previous entry is valid
172 PageTable::iterator i = lookupTable.find(table[Index].VPN);
173 lookupTable.erase(i);
174 }
175 table[Index]=pte;
176
177 // Update fast lookup table
178 lookupTable.insert(make_pair(table[Index].VPN, Index));
179 }
180}
181
182// insert a new TLB entry
183void
184TLB::insert(Addr addr, PowerISA::PTE &pte)
185{
186 fatal("TLB Insert not yet implemented\n");
187}
188
189void
190TLB::flushAll()
191{
192 DPRINTF(TLB, "flushAll\n");
193 memset(table, 0, sizeof(PowerISA::PTE[size]));
194 lookupTable.clear();
195 nlu = 0;
196}
197
198void
199TLB::serialize(ostream &os)
200{
201 SERIALIZE_SCALAR(size);
202 SERIALIZE_SCALAR(nlu);
203
204 for (int i = 0; i < size; i++) {
205 nameOut(os, csprintf("%s.PTE%d", name(), i));
206 table[i].serialize(os);
207 }
208}
209
210void
211TLB::unserialize(Checkpoint *cp, const string &section)
212{
213 UNSERIALIZE_SCALAR(size);
214 UNSERIALIZE_SCALAR(nlu);
215
216 for (int i = 0; i < size; i++) {
217 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
218 if (table[i].V0 || table[i].V1) {
219 lookupTable.insert(make_pair(table[i].VPN, i));
220 }
221 }
222}
223
224void
225TLB::regStats()
226{
227 read_hits
228 .name(name() + ".read_hits")
229 .desc("DTB read hits")
230 ;
231
232 read_misses
233 .name(name() + ".read_misses")
234 .desc("DTB read misses")
235 ;
236
237
238 read_accesses
239 .name(name() + ".read_accesses")
240 .desc("DTB read accesses")
241 ;
242
243 write_hits
244 .name(name() + ".write_hits")
245 .desc("DTB write hits")
246 ;
247
248 write_misses
249 .name(name() + ".write_misses")
250 .desc("DTB write misses")
251 ;
252
253
254 write_accesses
255 .name(name() + ".write_accesses")
256 .desc("DTB write accesses")
257 ;
258
259 hits
260 .name(name() + ".hits")
261 .desc("DTB hits")
262 ;
263
264 misses
265 .name(name() + ".misses")
266 .desc("DTB misses")
267 ;
268
269 accesses
270 .name(name() + ".accesses")
271 .desc("DTB accesses")
272 ;
273
274 hits = read_hits + write_hits;
275 misses = read_misses + write_misses;
276 accesses = read_accesses + write_accesses;
277}
278
279Fault
280TLB::translateInst(RequestPtr req, ThreadContext *tc)
281{
282 // Instruction accesses must be word-aligned
283 if (req->getVaddr() & 0x3) {
284 DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
285 req->getSize());
286 return new AlignmentFault();
287 }
288
289 Process * p = tc->getProcessPtr();
290
291 Fault fault = p->pTable->translate(req);
292 if (fault != NoFault)
293 return fault;
294
295 return NoFault;
296}
297
298Fault
299TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
300{
301 Process * p = tc->getProcessPtr();
302
303 Fault fault = p->pTable->translate(req);
304 if (fault != NoFault)
305 return fault;
306
307 return NoFault;
308}
309
310Fault
311TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
312{
313#if !FULL_SYSTEM
314 if (mode == Execute)
315 return translateInst(req, tc);
316 else
317 return translateData(req, tc, mode == Write);
318#else
319 fatal("translate atomic not yet implemented\n");
320#endif
321}
322
323void
324TLB::translateTiming(RequestPtr req, ThreadContext *tc,
325 Translation *translation, Mode mode)
326{
327 assert(translation);
328 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
329}
330
331PowerISA::PTE &
332TLB::index(bool advance)
333{
334 PowerISA::PTE *pte = &table[nlu];
335
336 if (advance)
337 nextnlu();
338
339 return *pte;
340}
341
342PowerISA::TLB *
343PowerTLBParams::create()
344{
345 return new PowerISA::TLB(this);
346}