tlb.hh (8888:befcf4d79fc1) | tlb.hh (9738:304a37519d11) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 104 unchanged lines hidden (view full) --- 113 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 114 void translateTiming(RequestPtr req, ThreadContext *tc, 115 Translation *translation, Mode mode); 116 117 /** Function stub for CheckerCPU compilation issues. MIPS does not 118 * support the Checker model at the moment. 119 */ 120 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 104 unchanged lines hidden (view full) --- 113 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 114 void translateTiming(RequestPtr req, ThreadContext *tc, 115 Translation *translation, Mode mode); 116 117 /** Function stub for CheckerCPU compilation issues. MIPS does not 118 * support the Checker model at the moment. 119 */ 120 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); |
121 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; |
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121 122 private: 123 Fault translateInst(RequestPtr req, ThreadContext *tc); 124 Fault translateData(RequestPtr req, ThreadContext *tc, bool write); 125}; 126 127} 128 129 130 131#endif // __MIPS_MEMORY_HH__ | 122 123 private: 124 Fault translateInst(RequestPtr req, ThreadContext *tc); 125 Fault translateData(RequestPtr req, ThreadContext *tc, bool write); 126}; 127 128} 129 130 131 132#endif // __MIPS_MEMORY_HH__ |