tlb.hh (5999:3cf8e71257e0) | tlb.hh (6022:410194bb3049) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 29 unchanged lines hidden (view full) --- 38#include <map> 39 40#include "arch/mips/isa_traits.hh" 41#include "arch/mips/utility.hh" 42#include "arch/mips/vtophys.hh" 43#include "arch/mips/pagetable.hh" 44#include "base/statistics.hh" 45#include "mem/request.hh" | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 29 unchanged lines hidden (view full) --- 38#include <map> 39 40#include "arch/mips/isa_traits.hh" 41#include "arch/mips/utility.hh" 42#include "arch/mips/vtophys.hh" 43#include "arch/mips/pagetable.hh" 44#include "base/statistics.hh" 45#include "mem/request.hh" |
46#include "params/MipsDTB.hh" 47#include "params/MipsITB.hh" | 46#include "params/MipsTLB.hh" |
48#include "sim/faults.hh" 49#include "sim/tlb.hh" 50#include "sim/sim_object.hh" 51 52class ThreadContext; 53 54/* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB 55 However, to maintain compatibility with other architectures, we'll --- 77 unchanged lines hidden (view full) --- 133 134 static Fault checkCacheability(RequestPtr &req); 135 136 // Checkpointing 137 void serialize(std::ostream &os); 138 void unserialize(Checkpoint *cp, const std::string §ion); 139 140 void regStats(); | 47#include "sim/faults.hh" 48#include "sim/tlb.hh" 49#include "sim/sim_object.hh" 50 51class ThreadContext; 52 53/* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB 54 However, to maintain compatibility with other architectures, we'll --- 77 unchanged lines hidden (view full) --- 132 133 static Fault checkCacheability(RequestPtr &req); 134 135 // Checkpointing 136 void serialize(std::ostream &os); 137 void unserialize(Checkpoint *cp, const std::string §ion); 138 139 void regStats(); |
141}; | |
142 | 140 |
143class ITB : public TLB { 144 public: 145 typedef MipsTLBParams Params; 146 ITB(const Params *p); 147 148 Fault translateAtomic(RequestPtr req, ThreadContext *tc); 149 void translateTiming(RequestPtr req, ThreadContext *tc, 150 Translation *translation); 151}; 152 153class DTB : public TLB { 154 public: 155 typedef MipsTLBParams Params; 156 DTB(const Params *p); 157 | |
158 Fault translateAtomic(RequestPtr req, ThreadContext *tc, | 141 Fault translateAtomic(RequestPtr req, ThreadContext *tc, |
159 bool write = false); | 142 bool write=false, bool execute=false); |
160 void translateTiming(RequestPtr req, ThreadContext *tc, | 143 void translateTiming(RequestPtr req, ThreadContext *tc, |
161 Translation *translation, bool write = false); 162}; | 144 Translation *translation, bool write=false, bool execute=false); |
163 | 145 |
164class UTB : public ITB, public DTB { 165 public: 166 typedef MipsTLBParams Params; 167 UTB(const Params *p); 168 | 146 private: 147 Fault translateInst(RequestPtr req, ThreadContext *tc); 148 Fault translateData(RequestPtr req, ThreadContext *tc, bool write); |
169}; 170 171} 172 173 174 175#endif // __MIPS_MEMORY_HH__ | 149}; 150 151} 152 153 154 155#endif // __MIPS_MEMORY_HH__ |