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< * Copyright (c) 2006 The Regents of The University of Michigan
---
> * Copyright (c) 2007 MIPS Technologies, Inc.
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< * Authors: Gabe Black
---
> * Authors: Jaidev Patwardhan
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> #include <map>
>
> #include "arch/mips/isa_traits.hh"
> #include "arch/mips/utility.hh"
> #include "arch/mips/vtophys.hh"
> #include "arch/mips/pagetable.hh"
> #include "base/statistics.hh"
> #include "mem/request.hh"
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> #include "sim/faults.hh"
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> #include "sim/sim_object.hh"
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< namespace MipsISA
< {
< struct TlbEntry
< {
< Addr _pageStart;
< TlbEntry() {}
< TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
---
> class ThreadContext;
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< Addr pageStart()
< {
< return _pageStart;
< }
---
> /* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB
> However, to maintain compatibility with other architectures, we'll
> simply create an ITLB and DTLB that will point to the real TLB */
> namespace MipsISA {
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< void serialize(std::ostream &os);
< void unserialize(Checkpoint *cp, const std::string &section);
< };
---
> // WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
> // We just need this to make compiler happy. Use "PTE" type for real entry.
> struct TlbEntry
> {
> Addr _pageStart;
> TlbEntry() {}
> TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
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< class TLB : public GenericTLB
---
> Addr pageStart()
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< public:
< typedef MipsTLBParams Params;
< TLB(const Params *p) : GenericTLB(p)
< {}
---
> return _pageStart;
> }
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< Fault translate(RequestPtr req, ThreadContext *tc, bool=false);
< };
<
< class ITB : public TLB
---
> void serialize(std::ostream &os)
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< public:
< typedef MipsITBParams Params;
< ITB(const Params *p) : TLB(p)
< {}
< };
---
> SERIALIZE_SCALAR(_pageStart);
> }
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< class DTB : public TLB
---
> void unserialize(Checkpoint *cp, const std::string &section)
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< public:
< typedef MipsDTBParams Params;
< DTB(const Params *p) : TLB(p)
< {}
< };
---
> UNSERIALIZE_SCALAR(_pageStart);
> }
>
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< #endif // __ARCH_MIPS_TLB_HH__
---
> class TLB : public SimObject
> {
> protected:
> typedef std::multimap<Addr, int> PageTable;
> PageTable lookupTable; // Quick lookup into page table
>
> MipsISA::PTE *table; // the Page Table
> int size; // TLB Size
> int nlu; // not last used entry (for replacement)
>
> void nextnlu() { if (++nlu >= size) nlu = 0; }
> MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
>
> mutable Stats::Scalar<> read_hits;
> mutable Stats::Scalar<> read_misses;
> mutable Stats::Scalar<> read_acv;
> mutable Stats::Scalar<> read_accesses;
> mutable Stats::Scalar<> write_hits;
> mutable Stats::Scalar<> write_misses;
> mutable Stats::Scalar<> write_acv;
> mutable Stats::Scalar<> write_accesses;
> Stats::Formula hits;
> Stats::Formula misses;
> Stats::Formula invalids;
> Stats::Formula accesses;
>
> public:
> typedef MipsTLBParams Params;
> TLB(const Params *p);
>
> int probeEntry(Addr vpn,uint8_t) const;
> MipsISA::PTE *getEntry(unsigned) const;
> virtual ~TLB();
> int smallPages;
> int getsize() const { return size; }
>
> MipsISA::PTE &index(bool advance = true);
> void insert(Addr vaddr, MipsISA::PTE &pte);
> void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
> void flushAll();
>
> // static helper functions... really
> static bool validVirtualAddress(Addr vaddr);
>
> static Fault checkCacheability(RequestPtr &req);
>
> // Checkpointing
> void serialize(std::ostream &os);
> void unserialize(Checkpoint *cp, const std::string &section);
>
> void regStats();
> };
>
> class ITB : public TLB {
> public:
> typedef MipsTLBParams Params;
> ITB(const Params *p);
>
> Fault translate(RequestPtr &req, ThreadContext *tc);
> };
>
> class DTB : public TLB {
> public:
> typedef MipsTLBParams Params;
> DTB(const Params *p);
>
> Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false);
> };
>
> class UTB : public ITB, public DTB {
> public:
> typedef MipsTLBParams Params;
> UTB(const Params *p);
>
> };
>
> }
>
>
>
> #endif // __MIPS_MEMORY_HH__