1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 * Steve Reinhardt
31 * Jaidev Patwardhan
32 * Korey Sewell
33 */
34
35#ifndef __ARCH_MIPS_TLB_HH__
36#define __ARCH_MIPS_TLB_HH__
37
38#include <map>
39
40#include "arch/mips/isa_traits.hh"
41#include "arch/mips/utility.hh"
42#include "arch/mips/vtophys.hh"
43#include "arch/mips/pagetable.hh"
44#include "base/statistics.hh"
45#include "mem/request.hh"
46#include "params/MipsDTB.hh"
47#include "params/MipsITB.hh"
48#include "sim/faults.hh"
49#include "sim/tlb.hh"
50#include "sim/sim_object.hh"
51
52class ThreadContext;
53
54/* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB
55 However, to maintain compatibility with other architectures, we'll
56 simply create an ITLB and DTLB that will point to the real TLB */
57namespace MipsISA {
58
59// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
60struct TlbEntry
61{
62 Addr _pageStart;
63 TlbEntry() {}
64 TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
65
66 Addr pageStart()
67 {
68 return _pageStart;
69 }
70
71 void
72 updateVaddr(Addr new_vaddr) {}
73
74 void serialize(std::ostream &os)
75 {
76 SERIALIZE_SCALAR(_pageStart);
77 }
78
79 void unserialize(Checkpoint *cp, const std::string §ion)
80 {
81 UNSERIALIZE_SCALAR(_pageStart);
82 }
83
84};
85
86class TLB : public BaseTLB
87{
88 protected:
89 typedef std::multimap<Addr, int> PageTable;
90 PageTable lookupTable; // Quick lookup into page table
91
92 MipsISA::PTE *table; // the Page Table
93 int size; // TLB Size
94 int nlu; // not last used entry (for replacement)
95
96 void nextnlu() { if (++nlu >= size) nlu = 0; }
97 MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
98
99 mutable Stats::Scalar<> read_hits;
100 mutable Stats::Scalar<> read_misses;
101 mutable Stats::Scalar<> read_acv;
102 mutable Stats::Scalar<> read_accesses;
103 mutable Stats::Scalar<> write_hits;
104 mutable Stats::Scalar<> write_misses;
105 mutable Stats::Scalar<> write_acv;
106 mutable Stats::Scalar<> write_accesses;
107 Stats::Formula hits;
108 Stats::Formula misses;
109 Stats::Formula invalids;
110 Stats::Formula accesses;
111
112 public:
113 typedef MipsTLBParams Params;
114 TLB(const Params *p);
115
116 int probeEntry(Addr vpn,uint8_t) const;
117 MipsISA::PTE *getEntry(unsigned) const;
118 virtual ~TLB();
119 int smallPages;
120 int getsize() const { return size; }
121
122 MipsISA::PTE &index(bool advance = true);
123 void insert(Addr vaddr, MipsISA::PTE &pte);
124 void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
125 void flushAll();
126 void demapPage(Addr vaddr, uint64_t asn)
127 {
128 panic("demapPage unimplemented.\n");
129 }
130
131 // static helper functions... really
132 static bool validVirtualAddress(Addr vaddr);
133
134 static Fault checkCacheability(RequestPtr &req);
135
136 // Checkpointing
137 void serialize(std::ostream &os);
138 void unserialize(Checkpoint *cp, const std::string §ion);
139
140 void regStats();
141};
142
143class ITB : public TLB {
144 public:
145 typedef MipsTLBParams Params;
146 ITB(const Params *p);
147
| 1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 * Steve Reinhardt
31 * Jaidev Patwardhan
32 * Korey Sewell
33 */
34
35#ifndef __ARCH_MIPS_TLB_HH__
36#define __ARCH_MIPS_TLB_HH__
37
38#include <map>
39
40#include "arch/mips/isa_traits.hh"
41#include "arch/mips/utility.hh"
42#include "arch/mips/vtophys.hh"
43#include "arch/mips/pagetable.hh"
44#include "base/statistics.hh"
45#include "mem/request.hh"
46#include "params/MipsDTB.hh"
47#include "params/MipsITB.hh"
48#include "sim/faults.hh"
49#include "sim/tlb.hh"
50#include "sim/sim_object.hh"
51
52class ThreadContext;
53
54/* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB
55 However, to maintain compatibility with other architectures, we'll
56 simply create an ITLB and DTLB that will point to the real TLB */
57namespace MipsISA {
58
59// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
60struct TlbEntry
61{
62 Addr _pageStart;
63 TlbEntry() {}
64 TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
65
66 Addr pageStart()
67 {
68 return _pageStart;
69 }
70
71 void
72 updateVaddr(Addr new_vaddr) {}
73
74 void serialize(std::ostream &os)
75 {
76 SERIALIZE_SCALAR(_pageStart);
77 }
78
79 void unserialize(Checkpoint *cp, const std::string §ion)
80 {
81 UNSERIALIZE_SCALAR(_pageStart);
82 }
83
84};
85
86class TLB : public BaseTLB
87{
88 protected:
89 typedef std::multimap<Addr, int> PageTable;
90 PageTable lookupTable; // Quick lookup into page table
91
92 MipsISA::PTE *table; // the Page Table
93 int size; // TLB Size
94 int nlu; // not last used entry (for replacement)
95
96 void nextnlu() { if (++nlu >= size) nlu = 0; }
97 MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
98
99 mutable Stats::Scalar<> read_hits;
100 mutable Stats::Scalar<> read_misses;
101 mutable Stats::Scalar<> read_acv;
102 mutable Stats::Scalar<> read_accesses;
103 mutable Stats::Scalar<> write_hits;
104 mutable Stats::Scalar<> write_misses;
105 mutable Stats::Scalar<> write_acv;
106 mutable Stats::Scalar<> write_accesses;
107 Stats::Formula hits;
108 Stats::Formula misses;
109 Stats::Formula invalids;
110 Stats::Formula accesses;
111
112 public:
113 typedef MipsTLBParams Params;
114 TLB(const Params *p);
115
116 int probeEntry(Addr vpn,uint8_t) const;
117 MipsISA::PTE *getEntry(unsigned) const;
118 virtual ~TLB();
119 int smallPages;
120 int getsize() const { return size; }
121
122 MipsISA::PTE &index(bool advance = true);
123 void insert(Addr vaddr, MipsISA::PTE &pte);
124 void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
125 void flushAll();
126 void demapPage(Addr vaddr, uint64_t asn)
127 {
128 panic("demapPage unimplemented.\n");
129 }
130
131 // static helper functions... really
132 static bool validVirtualAddress(Addr vaddr);
133
134 static Fault checkCacheability(RequestPtr &req);
135
136 // Checkpointing
137 void serialize(std::ostream &os);
138 void unserialize(Checkpoint *cp, const std::string §ion);
139
140 void regStats();
141};
142
143class ITB : public TLB {
144 public:
145 typedef MipsTLBParams Params;
146 ITB(const Params *p);
147
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