isa_traits.hh (6216:2f4020838149) | isa_traits.hh (6329:5d8b91875859) |
---|---|
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 129 unchanged lines hidden (view full) --- 138 INTLEVEL_IRQ2 = 22, 139 INTLEVEL_IRQ3 = 23, 140 141 INTLEVEL_SERIAL = 33, 142 143 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 144 }; 145 | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 129 unchanged lines hidden (view full) --- 138 INTLEVEL_IRQ2 = 22, 139 INTLEVEL_IRQ3 = 23, 140 141 INTLEVEL_SERIAL = 33, 142 143 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 144 }; 145 |
146 | |
147 // MIPS modes 148 enum mode_type 149 { 150 mode_kernel = 0, // kernel 151 mode_supervisor = 1, // supervisor 152 mode_user = 2, // user mode 153 mode_debug = 3, // debug mode 154 mode_number // number of modes 155 }; 156 | 146 // MIPS modes 147 enum mode_type 148 { 149 mode_kernel = 0, // kernel 150 mode_supervisor = 1, // supervisor 151 mode_user = 2, // user mode 152 mode_debug = 3, // debug mode 153 mode_number // number of modes 154 }; 155 |
157 inline mode_type getOperatingMode(MiscReg Stat) 158 { 159 if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) 160 return mode_kernel; 161 else{ 162 if((Stat & 0x18) == 0x8) 163 return mode_supervisor; 164 else if((Stat & 0x18) == 0x10) 165 return mode_user; 166 else return mode_number; 167 } 168 } 169 170 | |
171 // return a no-op instruction... used for instruction fetch faults 172 const ExtMachInst NoopMachInst = 0x00000000; 173 | 156 // return a no-op instruction... used for instruction fetch faults 157 const ExtMachInst NoopMachInst = 0x00000000; 158 |
174 // Constants Related to the number of registers 175 const int NumIntArchRegs = 32; 176 const int NumIntSpecialRegs = 9; 177 const int NumFloatArchRegs = 32; 178 const int NumFloatSpecialRegs = 5; 179 180 const int MaxShadowRegSets = 16; // Maximum number of shadow register sets 181 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 182 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// 183 184 // Static instruction parameters 185 const int MaxInstSrcRegs = 10; 186 const int MaxInstDestRegs = 8; 187 188 // semantically meaningful register indices 189 const int ZeroReg = 0; 190 const int AssemblerReg = 1; 191 const int SyscallSuccessReg = 7; 192 const int FirstArgumentReg = 4; 193 const int ReturnValueReg = 2; 194 195 const int KernelReg0 = 26; 196 const int KernelReg1 = 27; 197 const int GlobalPointerReg = 28; 198 const int StackPointerReg = 29; 199 const int FramePointerReg = 30; 200 const int ReturnAddressReg = 31; 201 202 const int SyscallPseudoReturnReg = 3; 203 | |
204 const int LogVMPageSize = 13; // 8K bytes 205 const int VMPageSize = (1 << LogVMPageSize); 206 207 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 208 209 const int MachineBytes = 4; 210 const int WordBytes = 4; 211 const int HalfwordBytes = 2; 212 const int ByteBytes = 1; 213 214 const int ANNOTE_NONE = 0; 215 const uint32_t ITOUCH_ANNOTE = 0xffffffff; | 159 const int LogVMPageSize = 13; // 8K bytes 160 const int VMPageSize = (1 << LogVMPageSize); 161 162 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 163 164 const int MachineBytes = 4; 165 const int WordBytes = 4; 166 const int HalfwordBytes = 2; 167 const int ByteBytes = 1; 168 169 const int ANNOTE_NONE = 0; 170 const uint32_t ITOUCH_ANNOTE = 0xffffffff; |
216 217 // These help enumerate all the registers for dependence tracking. 218 const int FP_Base_DepTag = NumIntRegs; 219 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; 220 221 // Enumerate names for 'Control' Registers in the CPU 222 // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 223 // (Register Number-Register Select) Summary of Register 224 //------------------------------------------------------ 225 // The first set of names classify the CP0 names as Register Banks 226 // for easy indexing when using the 'RD + SEL' index combination 227 // in CP0 instructions. 228 enum MiscRegTags { 229 Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3 230 MVPControl, 231 MVPConf0, 232 MVPConf1, 233 234 CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15 235 VPEControl, 236 VPEConf0, 237 VPEConf1, 238 YQMask, 239 VPESchedule, 240 VPEScheFBack, 241 VPEOpt, 242 243 EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23 244 TCStatus, 245 TCBind, 246 TCRestart, 247 TCHalt, 248 TCContext, 249 TCSchedule, 250 TCScheFBack, 251 252 EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24 253 254 Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33 255 ContextConfig, 256 257 PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41 258 PageGrain = Ctrl_Base_DepTag + 41, 259 260 Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55 261 SRSConf0, 262 SRSConf1, 263 SRSConf2, 264 SRSConf3, 265 SRSConf4, 266 267 HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63 268 269 BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71 270 271 Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79 272 273 EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87 274 275 Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95 276 277 Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103 278 IntCtl, 279 SRSCtl, 280 SRSMap, 281 282 Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111 283 284 EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119 285 286 PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127, 287 EBase, 288 289 Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135 290 Config1, 291 Config2, 292 Config3, 293 Config4, 294 Config5, 295 Config6, 296 Config7, 297 298 299 LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143 300 301 WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151 302 WatchLo1, 303 WatchLo2, 304 WatchLo3, 305 WatchLo4, 306 WatchLo5, 307 WatchLo6, 308 WatchLo7, 309 310 WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159 311 WatchHi1, 312 WatchHi2, 313 WatchHi3, 314 WatchHi4, 315 WatchHi5, 316 WatchHi6, 317 WatchHi7, 318 319 XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167 320 321 //Bank 21: 168-175 322 323 //Bank 22: 176-183 324 325 Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191 326 TraceControl1, 327 TraceControl2, 328 UserTraceData, 329 TraceBPC, 330 331 DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199 332 333 PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207 334 PerfCnt1, 335 PerfCnt2, 336 PerfCnt3, 337 PerfCnt4, 338 PerfCnt5, 339 PerfCnt6, 340 PerfCnt7, 341 342 ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215 343 344 CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223 345 CacheErr1, 346 CacheErr2, 347 CacheErr3, 348 349 TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231 350 DataLo1, 351 TagLo2, 352 DataLo3, 353 TagLo4, 354 DataLo5, 355 TagLo6, 356 DataLo7, 357 358 TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239 359 DataHi1, 360 TagHi2, 361 DataHi3, 362 TagHi4, 363 DataHi5, 364 TagHi6, 365 DataHi7, 366 367 368 ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247 369 370 DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256 371 372 LLFlag = Ctrl_Base_DepTag + 257, 373 374 NumControlRegs 375 }; 376 377 const int TotalDataRegs = NumIntRegs + NumFloatRegs; 378 379 const int NumMiscRegs = NumControlRegs; 380 381 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 382 383 | |
384}; 385 386#endif // __ARCH_MIPS_ISA_TRAITS_HH__ | 171}; 172 173#endif // __ARCH_MIPS_ISA_TRAITS_HH__ |