isa_traits.hh (5543:3af77710f397) isa_traits.hh (5585:45233156c3cc)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 167 unchanged lines hidden (view full) ---

176 const int NumIntSpecialRegs = 9;
177 const int NumFloatArchRegs = 32;
178 const int NumFloatSpecialRegs = 5;
179
180 const int NumShadowRegSets = 16; // Maximum number of shadow register sets
181 const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs; //HI & LO Regs
182 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
183
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 167 unchanged lines hidden (view full) ---

176 const int NumIntSpecialRegs = 9;
177 const int NumFloatArchRegs = 32;
178 const int NumFloatSpecialRegs = 5;
179
180 const int NumShadowRegSets = 16; // Maximum number of shadow register sets
181 const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs; //HI & LO Regs
182 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
183
184 const int TotalArchRegs = NumIntArchRegs * NumShadowRegSets;
185
184 // Static instruction parameters
185 const int MaxInstSrcRegs = 10;
186 const int MaxInstDestRegs = 8;
187
188 // semantically meaningful register indices
189 const int ZeroReg = 0;
190 const int AssemblerReg = 1;
191 const int ReturnValueReg = 2;

--- 205 unchanged lines hidden --- 		186 // Static instruction parameters
187 const int MaxInstSrcRegs = 10;
188 const int MaxInstDestRegs = 8;
189
190 // semantically meaningful register indices
191 const int ZeroReg = 0;
192 const int AssemblerReg = 1;
193 const int ReturnValueReg = 2;

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