isa_traits.hh (4772:f08370a81812) isa_traits.hh (5222:bb733a878f85)
1/*
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
2 * Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
4 *
3 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
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11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
4 * This software is part of the M5 simulator.
15 *
5 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6 * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
7 * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
8 * TO THESE TERMS AND CONDITIONS.
27 *
9 *
28 * Authors: Gabe Black
29 * Korey Sewell
10 * Permission is granted to use, copy, create derivative works and
11 * distribute this software and such derivative works for any purpose,
12 * so long as (1) the copyright notice above, this grant of permission,
13 * and the disclaimer below appear in all copies and derivative works
14 * made, (2) the copyright notice above is augmented as appropriate to
15 * reflect the addition of any new copyrightable work in a derivative
16 * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
17 * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
18 * advertising or publicity pertaining to the use or distribution of
19 * this software without specific, written prior authorization.
20 *
21 * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
22 * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
23 * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
25 * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
26 * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
27 * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
28 * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
29 * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
30 * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
31 * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
32 * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
33 *
34 * Authors: Gabe M. Black
35 * Korey L. Sewell
36 * Jaidev Patwardhan
30 */
31
32#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
33#define __ARCH_MIPS_ISA_TRAITS_HH__
34
35#include "arch/mips/types.hh"
37 */
38
39#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
40#define __ARCH_MIPS_ISA_TRAITS_HH__
41
42#include "arch/mips/types.hh"
43#include "config/full_system.hh"
36#include "sim/host.hh"
37
38namespace LittleEndianGuest {};
39
40#define TARGET_MIPS
41
42class StaticInstPtr;
43
44namespace MipsISA
45{
46 using namespace LittleEndianGuest;
47
48 StaticInstPtr decodeInst(ExtMachInst);
49
44#include "sim/host.hh"
45
46namespace LittleEndianGuest {};
47
48#define TARGET_MIPS
49
50class StaticInstPtr;
51
52namespace MipsISA
53{
54 using namespace LittleEndianGuest;
55
56 StaticInstPtr decodeInst(ExtMachInst);
57
50 // MIPS DOES a delay slot
58 // MIPS DOES have a delay slot
51 #define ISA_HAS_DELAY_SLOT 1
52
53 const Addr PageShift = 13;
54 const Addr PageBytes = ULL(1) << PageShift;
59 #define ISA_HAS_DELAY_SLOT 1
60
61 const Addr PageShift = 13;
62 const Addr PageBytes = ULL(1) << PageShift;
55 const Addr PageMask = ~(PageBytes - 1);
63 const Addr Page_Mask = ~(PageBytes - 1);
56 const Addr PageOffset = PageBytes - 1;
57
64 const Addr PageOffset = PageBytes - 1;
65
66
67 ////////////////////////////////////////////////////////////////////////
68 //
69 // Translation stuff
70 //
71
72 const Addr PteShift = 3;
73 const Addr NPtePageShift = PageShift - PteShift;
74 const Addr NPtePage = ULL(1) << NPtePageShift;
75 const Addr PteMask = NPtePage - 1;
76
77 //// All 'Mapped' segments go through the TLB
78 //// All other segments are translated by dropping the MSB, to give
79 //// the corresponding physical address
80 // User Segment - Mapped
81 const Addr USegBase = ULL(0x0);
82 const Addr USegEnd = ULL(0x7FFFFFFF);
83
84 // Kernel Segment 0 - Unmapped
85 const Addr KSeg0End = ULL(0x9FFFFFFF);
86 const Addr KSeg0Base = ULL(0x80000000);
87 const Addr KSeg0Mask = ULL(0x1FFFFFFF);
88
89 // Kernel Segment 1 - Unmapped, Uncached
90 const Addr KSeg1End = ULL(0xBFFFFFFF);
91 const Addr KSeg1Base = ULL(0xA0000000);
92 const Addr KSeg1Mask = ULL(0x1FFFFFFF);
93
94 // Kernel/Supervisor Segment - Mapped
95 const Addr KSSegEnd = ULL(0xDFFFFFFF);
96 const Addr KSSegBase = ULL(0xC0000000);
97
98 // Kernel Segment 3 - Mapped
99 const Addr KSeg3End = ULL(0xFFFFFFFF);
100 const Addr KSeg3Base = ULL(0xE0000000);
101
102
103 // For loading... XXX This maybe could be USegEnd?? --ali
104 const Addr LoadAddrMask = ULL(0xffffffffff);
105
106 inline Addr Phys2K0Seg(Addr addr)
107 {
108 // if (addr & PAddrUncachedBit43) {
109// addr &= PAddrUncachedMask;
110// addr |= PAddrUncachedBit40;
111// }
112 return addr | KSeg0Base;
113 }
114
115 ////////////////////////////////////////////////////////////////////////
116 //
117 // Interrupt levels
118 //
119 enum InterruptLevels
120 {
121 INTLEVEL_SOFTWARE_MIN = 4,
122 INTLEVEL_SOFTWARE_MAX = 19,
123
124 INTLEVEL_EXTERNAL_MIN = 20,
125 INTLEVEL_EXTERNAL_MAX = 34,
126
127 INTLEVEL_IRQ0 = 20,
128 INTLEVEL_IRQ1 = 21,
129 INTINDEX_ETHERNET = 0,
130 INTINDEX_SCSI = 1,
131 INTLEVEL_IRQ2 = 22,
132 INTLEVEL_IRQ3 = 23,
133
134 INTLEVEL_SERIAL = 33,
135
136 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
137 };
138
139
140 // MIPS modes
141 enum mode_type
142 {
143 mode_kernel = 0, // kernel
144 mode_supervisor = 1, // supervisor
145 mode_user = 2, // user mode
146 mode_debug = 3, // debug mode
147 mode_number // number of modes
148 };
149
150 inline mode_type getOperatingMode(MiscReg Stat)
151 {
152 if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0)
153 return mode_kernel;
154 else{
155 if((Stat & 0x18) == 0x8)
156 return mode_supervisor;
157 else if((Stat & 0x18) == 0x10)
158 return mode_user;
159 else return mode_number;
160 }
161 }
162
163
58 // return a no-op instruction... used for instruction fetch faults
59 const ExtMachInst NoopMachInst = 0x00000000;
60
61 // Constants Related to the number of registers
62 const int NumIntArchRegs = 32;
63 const int NumIntSpecialRegs = 9;
64 const int NumFloatArchRegs = 32;
65 const int NumFloatSpecialRegs = 5;
66
164 // return a no-op instruction... used for instruction fetch faults
165 const ExtMachInst NoopMachInst = 0x00000000;
166
167 // Constants Related to the number of registers
168 const int NumIntArchRegs = 32;
169 const int NumIntSpecialRegs = 9;
170 const int NumFloatArchRegs = 32;
171 const int NumFloatSpecialRegs = 5;
172
173 const int NumShadowRegSets = 16; // Maximum number of shadow register sets
174 const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs; //HI & LO Regs
175 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
176
67 // Static instruction parameters
177 // Static instruction parameters
68 const int MaxInstSrcRegs = 5;
69 const int MaxInstDestRegs = 4;
178 const int MaxInstSrcRegs = 10;
179 const int MaxInstDestRegs = 8;
70
71 // semantically meaningful register indices
72 const int ZeroReg = 0;
73 const int AssemblerReg = 1;
74 const int ReturnValueReg = 2;
75 const int ReturnValueReg1 = 2;
76 const int ReturnValueReg2 = 3;
180
181 // semantically meaningful register indices
182 const int ZeroReg = 0;
183 const int AssemblerReg = 1;
184 const int ReturnValueReg = 2;
185 const int ReturnValueReg1 = 2;
186 const int ReturnValueReg2 = 3;
77
78 const int ArgumentReg[] = {4, 5, 6, 7};
79 const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
80
187 const int ArgumentReg0 = 4;
188 const int ArgumentReg1 = 5;
189 const int ArgumentReg2 = 6;
190 const int ArgumentReg3 = 7;
81 const int KernelReg0 = 26;
82 const int KernelReg1 = 27;
83 const int GlobalPointerReg = 28;
84 const int StackPointerReg = 29;
85 const int FramePointerReg = 30;
86 const int ReturnAddressReg = 31;
87
191 const int KernelReg0 = 26;
192 const int KernelReg1 = 27;
193 const int GlobalPointerReg = 28;
194 const int StackPointerReg = 29;
195 const int FramePointerReg = 30;
196 const int ReturnAddressReg = 31;
197
198 const int ArgumentReg[] = {4, 5, 6, 7};
199 const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
200
88 const int SyscallNumReg = ReturnValueReg1;
89 const int SyscallPseudoReturnReg = ReturnValueReg2;
201 const int SyscallNumReg = ReturnValueReg1;
202 const int SyscallPseudoReturnReg = ReturnValueReg2;
90 const int SyscallSuccessReg = ArgumentReg[3];
203 const int SyscallSuccessReg = ArgumentReg3;
91
92 const int LogVMPageSize = 13; // 8K bytes
93 const int VMPageSize = (1 << LogVMPageSize);
94
95 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
96
97 const int MachineBytes = 4;
98 const int WordBytes = 4;
99 const int HalfwordBytes = 2;
100 const int ByteBytes = 1;
101
102 const int ANNOTE_NONE = 0;
103 const uint32_t ITOUCH_ANNOTE = 0xffffffff;
104
204
205 const int LogVMPageSize = 13; // 8K bytes
206 const int VMPageSize = (1 << LogVMPageSize);
207
208 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
209
210 const int MachineBytes = 4;
211 const int WordBytes = 4;
212 const int HalfwordBytes = 2;
213 const int ByteBytes = 1;
214
215 const int ANNOTE_NONE = 0;
216 const uint32_t ITOUCH_ANNOTE = 0xffffffff;
217
218 // These help enumerate all the registers for dependence tracking.
219 const int FP_Base_DepTag = NumIntRegs;
220 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
221
105 // Enumerate names for 'Control' Registers in the CPU
106 // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
107 // (Register Number-Register Select) Summary of Register
108 //------------------------------------------------------
109 // The first set of names classify the CP0 names as Register Banks
110 // for easy indexing when using the 'RD + SEL' index combination
111 // in CP0 instructions.
112 enum MiscRegTags {
222 // Enumerate names for 'Control' Registers in the CPU
223 // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
224 // (Register Number-Register Select) Summary of Register
225 //------------------------------------------------------
226 // The first set of names classify the CP0 names as Register Banks
227 // for easy indexing when using the 'RD + SEL' index combination
228 // in CP0 instructions.
229 enum MiscRegTags {
113 Index = 0, //Bank 0: 0 - 3
230 Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3
114 MVPControl,
115 MVPConf0,
116 MVPConf1,
117
231 MVPControl,
232 MVPConf0,
233 MVPConf1,
234
118 Random = 8, //Bank 1: 8 - 15
235 CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15
119 VPEControl,
120 VPEConf0,
121 VPEConf1,
122 YQMask,
123 VPESchedule,
124 VPEScheFBack,
125 VPEOpt,
126
236 VPEControl,
237 VPEConf0,
238 VPEConf1,
239 YQMask,
240 VPESchedule,
241 VPEScheFBack,
242 VPEOpt,
243
127 EntryLo0 = 16, //Bank 2: 16 - 23
244 EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23
128 TCStatus,
129 TCBind,
130 TCRestart,
131 TCHalt,
132 TCContext,
133 TCSchedule,
134 TCScheFBack,
135
245 TCStatus,
246 TCBind,
247 TCRestart,
248 TCHalt,
249 TCContext,
250 TCSchedule,
251 TCScheFBack,
252
136 EntryLo1 = 24, // Bank 3: 24
253 EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24
137
254
138 Context = 32, // Bank 4: 32 - 33
255 Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33
139 ContextConfig,
140
256 ContextConfig,
257
141 //PageMask = 40, //Bank 5: 40 - 41
142 PageGrain = 41,
258 PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
259 PageGrain = Ctrl_Base_DepTag + 41,
143
260
144 Wired = 48, //Bank 6:48-55
261 Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55
145 SRSConf0,
146 SRSConf1,
147 SRSConf2,
148 SRSConf3,
149 SRSConf4,
150
262 SRSConf0,
263 SRSConf1,
264 SRSConf2,
265 SRSConf3,
266 SRSConf4,
267
151 HWRena = 56, //Bank 7: 56-63
268 HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63
152
269
153 BadVAddr = 64, //Bank 8: 64-71
270 BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71
154
271
155 Count = 72, //Bank 9: 72-79
272 Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79
156
273
157 EntryHi = 80, //Bank 10: 80-87
274 EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87
158
275
159 Compare = 88, //Bank 11: 88-95
276 Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95
160
277
161 Status = 96, //Bank 12: 96-103
278 Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103
162 IntCtl,
163 SRSCtl,
164 SRSMap,
165
279 IntCtl,
280 SRSCtl,
281 SRSMap,
282
166 Cause = 104, //Bank 13: 104-111
283 Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111
167
284
168 EPC = 112, //Bank 14: 112-119
285 EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119
169
286
170 PRId = 120, //Bank 15: 120-127,
287 PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127,
171 EBase,
172
288 EBase,
289
173 Config = 128, //Bank 16: 128-135
290 Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135
174 Config1,
175 Config2,
176 Config3,
177 Config4,
178 Config5,
179 Config6,
180 Config7,
181
182
291 Config1,
292 Config2,
293 Config3,
294 Config4,
295 Config5,
296 Config6,
297 Config7,
298
299
183 LLAddr = 136, //Bank 17: 136-143
300 LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143
184
301
185 WatchLo0 = 144, //Bank 18: 144-151
302 WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151
186 WatchLo1,
187 WatchLo2,
188 WatchLo3,
189 WatchLo4,
190 WatchLo5,
191 WatchLo6,
192 WatchLo7,
193
303 WatchLo1,
304 WatchLo2,
305 WatchLo3,
306 WatchLo4,
307 WatchLo5,
308 WatchLo6,
309 WatchLo7,
310
194 WatchHi0 = 152, //Bank 19: 152-159
311 WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159
195 WatchHi1,
196 WatchHi2,
197 WatchHi3,
198 WatchHi4,
199 WatchHi5,
200 WatchHi6,
201 WatchHi7,
202
312 WatchHi1,
313 WatchHi2,
314 WatchHi3,
315 WatchHi4,
316 WatchHi5,
317 WatchHi6,
318 WatchHi7,
319
203 XCContext64 = 160, //Bank 20: 160-167
320 XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
204
205 //Bank 21: 168-175
206
207 //Bank 22: 176-183
208
321
322 //Bank 21: 168-175
323
324 //Bank 22: 176-183
325
209 Debug = 184, //Bank 23: 184-191
326 Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191
210 TraceControl1,
211 TraceControl2,
212 UserTraceData,
213 TraceBPC,
214
327 TraceControl1,
328 TraceControl2,
329 UserTraceData,
330 TraceBPC,
331
215 DEPC = 192, //Bank 24: 192-199
332 DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199
216
333
217 PerfCnt0 = 200, //Bank 25: 200-207
334 PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207
218 PerfCnt1,
219 PerfCnt2,
220 PerfCnt3,
221 PerfCnt4,
222 PerfCnt5,
223 PerfCnt6,
224 PerfCnt7,
225
335 PerfCnt1,
336 PerfCnt2,
337 PerfCnt3,
338 PerfCnt4,
339 PerfCnt5,
340 PerfCnt6,
341 PerfCnt7,
342
226 ErrCtl = 208, //Bank 26: 208-215
343 ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215
227
344
228 CacheErr0 = 216, //Bank 27: 216-223
345 CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223
229 CacheErr1,
230 CacheErr2,
231 CacheErr3,
232
346 CacheErr1,
347 CacheErr2,
348 CacheErr3,
349
233 TagLo0 = 224, //Bank 28: 224-231
350 TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231
234 DataLo1,
235 TagLo2,
236 DataLo3,
237 TagLo4,
238 DataLo5,
239 TagLo6,
240 DataLo7,
241
351 DataLo1,
352 TagLo2,
353 DataLo3,
354 TagLo4,
355 DataLo5,
356 TagLo6,
357 DataLo7,
358
242 TagHi0 = 232, //Bank 29: 232-239
359 TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239
243 DataHi1,
244 TagHi2,
245 DataHi3,
246 TagHi4,
247 DataHi5,
248 TagHi6,
249 DataHi7,
250
251
360 DataHi1,
361 TagHi2,
362 DataHi3,
363 TagHi4,
364 DataHi5,
365 TagHi6,
366 DataHi7,
367
368
252 ErrorEPC = 240, //Bank 30: 240-247
369 ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247
253
370
254 DESAVE = 248, //Bank 31: 248-256
371 DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256
255
372
256 LLFlag = 257,
373 LLFlag = Ctrl_Base_DepTag + 257,
257
258 NumControlRegs
259 };
260
374
375 NumControlRegs
376 };
377
261 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
262 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
378 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
379
263 const int NumMiscRegs = NumControlRegs;
264
265 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
266
380 const int NumMiscRegs = NumControlRegs;
381
382 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
383
267 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
268
384
269 // These help enumerate all the registers for dependence tracking.
270 const int FP_Base_DepTag = NumIntRegs;
271 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
272};
273
274using namespace MipsISA;
275
276#endif // __ARCH_MIPS_ISA_TRAITS_HH__
385};
386
387using namespace MipsISA;
388
389#endif // __ARCH_MIPS_ISA_TRAITS_HH__