isa_traits.hh (3093:b09c33e66bce) | isa_traits.hh (4661:44458219add1) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 46 unchanged lines hidden (view full) --- 55 const Addr PageMask = ~(PageBytes - 1); 56 const Addr PageOffset = PageBytes - 1; 57 58 // return a no-op instruction... used for instruction fetch faults 59 const ExtMachInst NoopMachInst = 0x00000000; 60 61 // Constants Related to the number of registers 62 const int NumIntArchRegs = 32; | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 46 unchanged lines hidden (view full) --- 55 const Addr PageMask = ~(PageBytes - 1); 56 const Addr PageOffset = PageBytes - 1; 57 58 // return a no-op instruction... used for instruction fetch faults 59 const ExtMachInst NoopMachInst = 0x00000000; 60 61 // Constants Related to the number of registers 62 const int NumIntArchRegs = 32; |
63 const int NumIntSpecialRegs = 2; | 63 const int NumIntSpecialRegs = 9; |
64 const int NumFloatArchRegs = 32; 65 const int NumFloatSpecialRegs = 5; | 64 const int NumFloatArchRegs = 32; 65 const int NumFloatSpecialRegs = 5; |
66 const int NumControlRegs = 265; 67 const int NumInternalProcRegs = 0; | |
68 | 66 |
69 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 70 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// 71 const int NumMiscRegs = NumControlRegs; 72 73 const int TotalNumRegs = NumIntRegs + NumFloatRegs + 74 NumMiscRegs + 0/*NumInternalProcRegs*/; 75 76 const int TotalDataRegs = NumIntRegs + NumFloatRegs; 77 | |
78 // Static instruction parameters | 67 // Static instruction parameters |
79 const int MaxInstSrcRegs = 3; 80 const int MaxInstDestRegs = 2; | 68 const int MaxInstSrcRegs = 5; 69 const int MaxInstDestRegs = 4; |
81 82 // semantically meaningful register indices 83 const int ZeroReg = 0; 84 const int AssemblerReg = 1; 85 const int ReturnValueReg = 2; 86 const int ReturnValueReg1 = 2; 87 const int ReturnValueReg2 = 3; 88 const int ArgumentReg0 = 4; 89 const int ArgumentReg1 = 5; 90 const int ArgumentReg2 = 6; 91 const int ArgumentReg3 = 7; 92 const int KernelReg0 = 26; 93 const int KernelReg1 = 27; 94 const int GlobalPointerReg = 28; 95 const int StackPointerReg = 29; 96 const int FramePointerReg = 30; 97 const int ReturnAddressReg = 31; 98 99 const int SyscallNumReg = ReturnValueReg1; | 70 71 // semantically meaningful register indices 72 const int ZeroReg = 0; 73 const int AssemblerReg = 1; 74 const int ReturnValueReg = 2; 75 const int ReturnValueReg1 = 2; 76 const int ReturnValueReg2 = 3; 77 const int ArgumentReg0 = 4; 78 const int ArgumentReg1 = 5; 79 const int ArgumentReg2 = 6; 80 const int ArgumentReg3 = 7; 81 const int KernelReg0 = 26; 82 const int KernelReg1 = 27; 83 const int GlobalPointerReg = 28; 84 const int StackPointerReg = 29; 85 const int FramePointerReg = 30; 86 const int ReturnAddressReg = 31; 87 88 const int SyscallNumReg = ReturnValueReg1; |
100 const int SyscallPseudoReturnReg = ReturnValueReg1; | 89 const int SyscallPseudoReturnReg = ReturnValueReg2; |
101 const int SyscallSuccessReg = ArgumentReg3; 102 103 const int LogVMPageSize = 13; // 8K bytes 104 const int VMPageSize = (1 << LogVMPageSize); 105 106 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 107 108 const int MachineBytes = 4; 109 const int WordBytes = 4; 110 const int HalfwordBytes = 2; 111 const int ByteBytes = 1; 112 | 90 const int SyscallSuccessReg = ArgumentReg3; 91 92 const int LogVMPageSize = 13; // 8K bytes 93 const int VMPageSize = (1 << LogVMPageSize); 94 95 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 96 97 const int MachineBytes = 4; 98 const int WordBytes = 4; 99 const int HalfwordBytes = 2; 100 const int ByteBytes = 1; 101 |
113 // These help enumerate all the registers for dependence tracking. 114 const int FP_Base_DepTag = 34; 115 const int Ctrl_Base_DepTag = 257; 116 | |
117 const int ANNOTE_NONE = 0; 118 const uint32_t ITOUCH_ANNOTE = 0xffffffff; 119 | 102 const int ANNOTE_NONE = 0; 103 const uint32_t ITOUCH_ANNOTE = 0xffffffff; 104 |
105 // Enumerate names for 'Control' Registers in the CPU 106 // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 107 // (Register Number-Register Select) Summary of Register 108 //------------------------------------------------------ 109 // The first set of names classify the CP0 names as Register Banks 110 // for easy indexing when using the 'RD + SEL' index combination 111 // in CP0 instructions. 112 enum MiscRegTags { 113 Index = 0, //Bank 0: 0 - 3 114 MVPControl, 115 MVPConf0, 116 MVPConf1, 117 118 Random = 8, //Bank 1: 8 - 15 119 VPEControl, 120 VPEConf0, 121 VPEConf1, 122 YQMask, 123 VPESchedule, 124 VPEScheFBack, 125 VPEOpt, 126 127 EntryLo0 = 16, //Bank 2: 16 - 23 128 TCStatus, 129 TCBind, 130 TCRestart, 131 TCHalt, 132 TCContext, 133 TCSchedule, 134 TCScheFBack, 135 136 EntryLo1 = 24, // Bank 3: 24 137 138 Context = 32, // Bank 4: 32 - 33 139 ContextConfig, 140 141 //PageMask = 40, //Bank 5: 40 - 41 142 PageGrain = 41, 143 144 Wired = 48, //Bank 6:48-55 145 SRSConf0, 146 SRSConf1, 147 SRSConf2, 148 SRSConf3, 149 SRSConf4, 150 151 HWRena = 56, //Bank 7: 56-63 152 153 BadVAddr = 64, //Bank 8: 64-71 154 155 Count = 72, //Bank 9: 72-79 156 157 EntryHi = 80, //Bank 10: 80-87 158 159 Compare = 88, //Bank 11: 88-95 160 161 Status = 96, //Bank 12: 96-103 162 IntCtl, 163 SRSCtl, 164 SRSMap, 165 166 Cause = 104, //Bank 13: 104-111 167 168 EPC = 112, //Bank 14: 112-119 169 170 PRId = 120, //Bank 15: 120-127, 171 EBase, 172 173 Config = 128, //Bank 16: 128-135 174 Config1, 175 Config2, 176 Config3, 177 Config4, 178 Config5, 179 Config6, 180 Config7, 181 182 183 LLAddr = 136, //Bank 17: 136-143 184 185 WatchLo0 = 144, //Bank 18: 144-151 186 WatchLo1, 187 WatchLo2, 188 WatchLo3, 189 WatchLo4, 190 WatchLo5, 191 WatchLo6, 192 WatchLo7, 193 194 WatchHi0 = 152, //Bank 19: 152-159 195 WatchHi1, 196 WatchHi2, 197 WatchHi3, 198 WatchHi4, 199 WatchHi5, 200 WatchHi6, 201 WatchHi7, 202 203 XCContext64 = 160, //Bank 20: 160-167 204 205 //Bank 21: 168-175 206 207 //Bank 22: 176-183 208 209 Debug = 184, //Bank 23: 184-191 210 TraceControl1, 211 TraceControl2, 212 UserTraceData, 213 TraceBPC, 214 215 DEPC = 192, //Bank 24: 192-199 216 217 PerfCnt0 = 200, //Bank 25: 200-207 218 PerfCnt1, 219 PerfCnt2, 220 PerfCnt3, 221 PerfCnt4, 222 PerfCnt5, 223 PerfCnt6, 224 PerfCnt7, 225 226 ErrCtl = 208, //Bank 26: 208-215 227 228 CacheErr0 = 216, //Bank 27: 216-223 229 CacheErr1, 230 CacheErr2, 231 CacheErr3, 232 233 TagLo0 = 224, //Bank 28: 224-231 234 DataLo1, 235 TagLo2, 236 DataLo3, 237 TagLo4, 238 DataLo5, 239 TagLo6, 240 DataLo7, 241 242 TagHi0 = 232, //Bank 29: 232-239 243 DataHi1, 244 TagHi2, 245 DataHi3, 246 TagHi4, 247 DataHi5, 248 TagHi6, 249 DataHi7, 250 251 252 ErrorEPC = 240, //Bank 30: 240-247 253 254 DESAVE = 248, //Bank 31: 248-256 255 256 LLFlag = 257, 257 258 NumControlRegs 259 }; 260 261 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 262 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// 263 const int NumMiscRegs = NumControlRegs; 264 265 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 266 267 const int TotalDataRegs = NumIntRegs + NumFloatRegs; 268 269 // These help enumerate all the registers for dependence tracking. 270 const int FP_Base_DepTag = NumIntRegs; 271 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; |
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120}; 121 122using namespace MipsISA; 123 124#endif // __ARCH_MIPS_ISA_TRAITS_HH__ | 272}; 273 274using namespace MipsISA; 275 276#endif // __ARCH_MIPS_ISA_TRAITS_HH__ |