isa_traits.hh (2665:a124942bacb8) | isa_traits.hh (2680:246e7104f744) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 34 unchanged lines hidden (view full) --- 43#include "sim/host.hh" 44#include "sim/faults.hh" 45 46#include <vector> 47 48class FastCPU; 49class FullCPU; 50class Checkpoint; | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 34 unchanged lines hidden (view full) --- 43#include "sim/host.hh" 44#include "sim/faults.hh" 45 46#include <vector> 47 48class FastCPU; 49class FullCPU; 50class Checkpoint; |
51class ExecContext; | 51class ThreadContext; |
52 53namespace LittleEndianGuest {}; 54 55#define TARGET_MIPS 56 57class StaticInst; 58class StaticInstPtr; 59 --- 66 unchanged lines hidden (view full) --- 126 return ext_inst; 127#else 128 return ExtMachInst(inst); 129#endif 130 } 131 132 /** 133 * Function to insure ISA semantics about 0 registers. | 52 53namespace LittleEndianGuest {}; 54 55#define TARGET_MIPS 56 57class StaticInst; 58class StaticInstPtr; 59 --- 66 unchanged lines hidden (view full) --- 126 return ext_inst; 127#else 128 return ExtMachInst(inst); 129#endif 130 } 131 132 /** 133 * Function to insure ISA semantics about 0 registers. |
134 * @param xc The execution context. | 134 * @param tc The thread context. |
135 */ | 135 */ |
136 template <class XC> 137 void zeroRegisters(XC *xc); | 136 template <class TC> 137 void zeroRegisters(TC *tc); |
138 139 const Addr MaxAddr = (Addr)-1; 140 | 138 139 const Addr MaxAddr = (Addr)-1; 140 |
141 void copyRegs(ExecContext *src, ExecContext *dest); | 141 void copyRegs(ThreadContext *src, ThreadContext *dest); |
142 143 uint64_t fpConvert(double fp_val, ConvertType cvt_type); 144 double roundFP(double val, int digits); 145 double truncFP(double val); 146 bool getFPConditionCode(uint32_t fcsr_reg, int cc); 147 uint32_t makeCCVector(uint32_t fcsr, int num, bool val); 148 149 // Machine operations --- 53 unchanged lines hidden --- | 142 143 uint64_t fpConvert(double fp_val, ConvertType cvt_type); 144 double roundFP(double val, int digits); 145 double truncFP(double val); 146 bool getFPConditionCode(uint32_t fcsr_reg, int cc); 147 uint32_t makeCCVector(uint32_t fcsr, int num, bool val); 148 149 // Machine operations --- 53 unchanged lines hidden --- |