2,3c2
< * Copyright (c) 2003-2005 The Regents of The University of Michigan
< * All rights reserved.
---
> * Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
5,14c4
< * Redistribution and use in source and binary forms, with or without
< * modification, are permitted provided that the following conditions are
< * met: redistributions of source code must retain the above copyright
< * notice, this list of conditions and the following disclaimer;
< * redistributions in binary form must reproduce the above copyright
< * notice, this list of conditions and the following disclaimer in the
< * documentation and/or other materials provided with the distribution;
< * neither the name of the copyright holders nor the names of its
< * contributors may be used to endorse or promote products derived from
< * this software without specific prior written permission.
---
> * This software is part of the M5 simulator.
16,26c6,8
< * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
< * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
< * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
< * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
< * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
< * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
< * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
< * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
< * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
< * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
< * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---
> * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
> * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
> * TO THESE TERMS AND CONDITIONS.
28,29c10,36
< * Authors: Gabe Black
< * Korey Sewell
---
> * Permission is granted to use, copy, create derivative works and
> * distribute this software and such derivative works for any purpose,
> * so long as (1) the copyright notice above, this grant of permission,
> * and the disclaimer below appear in all copies and derivative works
> * made, (2) the copyright notice above is augmented as appropriate to
> * reflect the addition of any new copyrightable work in a derivative
> * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
> * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
> * advertising or publicity pertaining to the use or distribution of
> * this software without specific, written prior authorization.
> *
> * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
> * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
> * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
> * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
> * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
> * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
> * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
> * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
> * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
> * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
> * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
> *
> * Authors: Gabe M. Black
> * Korey L. Sewell
> * Jaidev Patwardhan
35a43
> #include "config/full_system.hh"
50c58
< // MIPS DOES a delay slot
---
> // MIPS DOES have a delay slot
55c63
< const Addr PageMask = ~(PageBytes - 1);
---
> const Addr Page_Mask = ~(PageBytes - 1);
57a66,163
>
> ////////////////////////////////////////////////////////////////////////
> //
> // Translation stuff
> //
>
> const Addr PteShift = 3;
> const Addr NPtePageShift = PageShift - PteShift;
> const Addr NPtePage = ULL(1) << NPtePageShift;
> const Addr PteMask = NPtePage - 1;
>
> //// All 'Mapped' segments go through the TLB
> //// All other segments are translated by dropping the MSB, to give
> //// the corresponding physical address
> // User Segment - Mapped
> const Addr USegBase = ULL(0x0);
> const Addr USegEnd = ULL(0x7FFFFFFF);
>
> // Kernel Segment 0 - Unmapped
> const Addr KSeg0End = ULL(0x9FFFFFFF);
> const Addr KSeg0Base = ULL(0x80000000);
> const Addr KSeg0Mask = ULL(0x1FFFFFFF);
>
> // Kernel Segment 1 - Unmapped, Uncached
> const Addr KSeg1End = ULL(0xBFFFFFFF);
> const Addr KSeg1Base = ULL(0xA0000000);
> const Addr KSeg1Mask = ULL(0x1FFFFFFF);
>
> // Kernel/Supervisor Segment - Mapped
> const Addr KSSegEnd = ULL(0xDFFFFFFF);
> const Addr KSSegBase = ULL(0xC0000000);
>
> // Kernel Segment 3 - Mapped
> const Addr KSeg3End = ULL(0xFFFFFFFF);
> const Addr KSeg3Base = ULL(0xE0000000);
>
>
> // For loading... XXX This maybe could be USegEnd?? --ali
> const Addr LoadAddrMask = ULL(0xffffffffff);
>
> inline Addr Phys2K0Seg(Addr addr)
> {
> // if (addr & PAddrUncachedBit43) {
> // addr &= PAddrUncachedMask;
> // addr |= PAddrUncachedBit40;
> // }
> return addr | KSeg0Base;
> }
>
> ////////////////////////////////////////////////////////////////////////
> //
> // Interrupt levels
> //
> enum InterruptLevels
> {
> INTLEVEL_SOFTWARE_MIN = 4,
> INTLEVEL_SOFTWARE_MAX = 19,
>
> INTLEVEL_EXTERNAL_MIN = 20,
> INTLEVEL_EXTERNAL_MAX = 34,
>
> INTLEVEL_IRQ0 = 20,
> INTLEVEL_IRQ1 = 21,
> INTINDEX_ETHERNET = 0,
> INTINDEX_SCSI = 1,
> INTLEVEL_IRQ2 = 22,
> INTLEVEL_IRQ3 = 23,
>
> INTLEVEL_SERIAL = 33,
>
> NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
> };
>
>
> // MIPS modes
> enum mode_type
> {
> mode_kernel = 0, // kernel
> mode_supervisor = 1, // supervisor
> mode_user = 2, // user mode
> mode_debug = 3, // debug mode
> mode_number // number of modes
> };
>
> inline mode_type getOperatingMode(MiscReg Stat)
> {
> if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0)
> return mode_kernel;
> else{
> if((Stat & 0x18) == 0x8)
> return mode_supervisor;
> else if((Stat & 0x18) == 0x10)
> return mode_user;
> else return mode_number;
> }
> }
>
>
66a173,176
> const int NumShadowRegSets = 16; // Maximum number of shadow register sets
> const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs; //HI & LO Regs
> const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
>
68,69c178,179
< const int MaxInstSrcRegs = 5;
< const int MaxInstDestRegs = 4;
---
> const int MaxInstSrcRegs = 10;
> const int MaxInstDestRegs = 8;
77,80c187,190
<
< const int ArgumentReg[] = {4, 5, 6, 7};
< const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
<
---
> const int ArgumentReg0 = 4;
> const int ArgumentReg1 = 5;
> const int ArgumentReg2 = 6;
> const int ArgumentReg3 = 7;
87a198,200
> const int ArgumentReg[] = {4, 5, 6, 7};
> const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
>
90c203
< const int SyscallSuccessReg = ArgumentReg[3];
---
> const int SyscallSuccessReg = ArgumentReg3;
104a218,221
> // These help enumerate all the registers for dependence tracking.
> const int FP_Base_DepTag = NumIntRegs;
> const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
>
113c230
< Index = 0, //Bank 0: 0 - 3
---
> Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3
118c235
< Random = 8, //Bank 1: 8 - 15
---
> CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15
127c244
< EntryLo0 = 16, //Bank 2: 16 - 23
---
> EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23
136c253
< EntryLo1 = 24, // Bank 3: 24
---
> EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24
138c255
< Context = 32, // Bank 4: 32 - 33
---
> Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33
141,142c258,259
< //PageMask = 40, //Bank 5: 40 - 41
< PageGrain = 41,
---
> PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
> PageGrain = Ctrl_Base_DepTag + 41,
144c261
< Wired = 48, //Bank 6:48-55
---
> Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55
151c268
< HWRena = 56, //Bank 7: 56-63
---
> HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63
153c270
< BadVAddr = 64, //Bank 8: 64-71
---
> BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71
155c272
< Count = 72, //Bank 9: 72-79
---
> Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79
157c274
< EntryHi = 80, //Bank 10: 80-87
---
> EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87
159c276
< Compare = 88, //Bank 11: 88-95
---
> Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95
161c278
< Status = 96, //Bank 12: 96-103
---
> Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103
166c283
< Cause = 104, //Bank 13: 104-111
---
> Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111
168c285
< EPC = 112, //Bank 14: 112-119
---
> EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119
170c287
< PRId = 120, //Bank 15: 120-127,
---
> PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127,
173c290
< Config = 128, //Bank 16: 128-135
---
> Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135
183c300
< LLAddr = 136, //Bank 17: 136-143
---
> LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143
185c302
< WatchLo0 = 144, //Bank 18: 144-151
---
> WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151
194c311
< WatchHi0 = 152, //Bank 19: 152-159
---
> WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159
203c320
< XCContext64 = 160, //Bank 20: 160-167
---
> XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
209c326
< Debug = 184, //Bank 23: 184-191
---
> Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191
215c332
< DEPC = 192, //Bank 24: 192-199
---
> DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199
217c334
< PerfCnt0 = 200, //Bank 25: 200-207
---
> PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207
226c343
< ErrCtl = 208, //Bank 26: 208-215
---
> ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215
228c345
< CacheErr0 = 216, //Bank 27: 216-223
---
> CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223
233c350
< TagLo0 = 224, //Bank 28: 224-231
---
> TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231
242c359
< TagHi0 = 232, //Bank 29: 232-239
---
> TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239
252c369
< ErrorEPC = 240, //Bank 30: 240-247
---
> ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247
254c371
< DESAVE = 248, //Bank 31: 248-256
---
> DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256
256c373
< LLFlag = 257,
---
> LLFlag = Ctrl_Base_DepTag + 257,
261,262c378,379
< const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
< const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
---
> const int TotalDataRegs = NumIntRegs + NumFloatRegs;
>
267d383
< const int TotalDataRegs = NumIntRegs + NumFloatRegs;
269,271d384
< // These help enumerate all the registers for dependence tracking.
< const int FP_Base_DepTag = NumIntRegs;
< const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
< * Copyright (c) 2003-2005 The Regents of The University of Michigan
< * All rights reserved.
---
> * Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
5,14c4
< * Redistribution and use in source and binary forms, with or without
< * modification, are permitted provided that the following conditions are
< * met: redistributions of source code must retain the above copyright
< * notice, this list of conditions and the following disclaimer;
< * redistributions in binary form must reproduce the above copyright
< * notice, this list of conditions and the following disclaimer in the
< * documentation and/or other materials provided with the distribution;
< * neither the name of the copyright holders nor the names of its
< * contributors may be used to endorse or promote products derived from
< * this software without specific prior written permission.
---
> * This software is part of the M5 simulator.
16,26c6,8
< * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
< * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
< * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
< * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
< * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
< * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
< * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
< * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
< * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
< * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
< * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---
> * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
> * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
> * TO THESE TERMS AND CONDITIONS.
28,29c10,36
< * Authors: Gabe Black
< * Korey Sewell
---
> * Permission is granted to use, copy, create derivative works and
> * distribute this software and such derivative works for any purpose,
> * so long as (1) the copyright notice above, this grant of permission,
> * and the disclaimer below appear in all copies and derivative works
> * made, (2) the copyright notice above is augmented as appropriate to
> * reflect the addition of any new copyrightable work in a derivative
> * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
> * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
> * advertising or publicity pertaining to the use or distribution of
> * this software without specific, written prior authorization.
> *
> * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
> * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
> * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
> * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
> * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
> * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
> * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
> * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
> * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
> * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
> * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
> *
> * Authors: Gabe M. Black
> * Korey L. Sewell
> * Jaidev Patwardhan
35a43
> #include "config/full_system.hh"
50c58
< // MIPS DOES a delay slot
---
> // MIPS DOES have a delay slot
55c63
< const Addr PageMask = ~(PageBytes - 1);
---
> const Addr Page_Mask = ~(PageBytes - 1);
57a66,163
>
> ////////////////////////////////////////////////////////////////////////
> //
> // Translation stuff
> //
>
> const Addr PteShift = 3;
> const Addr NPtePageShift = PageShift - PteShift;
> const Addr NPtePage = ULL(1) << NPtePageShift;
> const Addr PteMask = NPtePage - 1;
>
> //// All 'Mapped' segments go through the TLB
> //// All other segments are translated by dropping the MSB, to give
> //// the corresponding physical address
> // User Segment - Mapped
> const Addr USegBase = ULL(0x0);
> const Addr USegEnd = ULL(0x7FFFFFFF);
>
> // Kernel Segment 0 - Unmapped
> const Addr KSeg0End = ULL(0x9FFFFFFF);
> const Addr KSeg0Base = ULL(0x80000000);
> const Addr KSeg0Mask = ULL(0x1FFFFFFF);
>
> // Kernel Segment 1 - Unmapped, Uncached
> const Addr KSeg1End = ULL(0xBFFFFFFF);
> const Addr KSeg1Base = ULL(0xA0000000);
> const Addr KSeg1Mask = ULL(0x1FFFFFFF);
>
> // Kernel/Supervisor Segment - Mapped
> const Addr KSSegEnd = ULL(0xDFFFFFFF);
> const Addr KSSegBase = ULL(0xC0000000);
>
> // Kernel Segment 3 - Mapped
> const Addr KSeg3End = ULL(0xFFFFFFFF);
> const Addr KSeg3Base = ULL(0xE0000000);
>
>
> // For loading... XXX This maybe could be USegEnd?? --ali
> const Addr LoadAddrMask = ULL(0xffffffffff);
>
> inline Addr Phys2K0Seg(Addr addr)
> {
> // if (addr & PAddrUncachedBit43) {
> // addr &= PAddrUncachedMask;
> // addr |= PAddrUncachedBit40;
> // }
> return addr | KSeg0Base;
> }
>
> ////////////////////////////////////////////////////////////////////////
> //
> // Interrupt levels
> //
> enum InterruptLevels
> {
> INTLEVEL_SOFTWARE_MIN = 4,
> INTLEVEL_SOFTWARE_MAX = 19,
>
> INTLEVEL_EXTERNAL_MIN = 20,
> INTLEVEL_EXTERNAL_MAX = 34,
>
> INTLEVEL_IRQ0 = 20,
> INTLEVEL_IRQ1 = 21,
> INTINDEX_ETHERNET = 0,
> INTINDEX_SCSI = 1,
> INTLEVEL_IRQ2 = 22,
> INTLEVEL_IRQ3 = 23,
>
> INTLEVEL_SERIAL = 33,
>
> NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
> };
>
>
> // MIPS modes
> enum mode_type
> {
> mode_kernel = 0, // kernel
> mode_supervisor = 1, // supervisor
> mode_user = 2, // user mode
> mode_debug = 3, // debug mode
> mode_number // number of modes
> };
>
> inline mode_type getOperatingMode(MiscReg Stat)
> {
> if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0)
> return mode_kernel;
> else{
> if((Stat & 0x18) == 0x8)
> return mode_supervisor;
> else if((Stat & 0x18) == 0x10)
> return mode_user;
> else return mode_number;
> }
> }
>
>
66a173,176
> const int NumShadowRegSets = 16; // Maximum number of shadow register sets
> const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs; //HI & LO Regs
> const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
>
68,69c178,179
< const int MaxInstSrcRegs = 5;
< const int MaxInstDestRegs = 4;
---
> const int MaxInstSrcRegs = 10;
> const int MaxInstDestRegs = 8;
77,80c187,190
<
< const int ArgumentReg[] = {4, 5, 6, 7};
< const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
<
---
> const int ArgumentReg0 = 4;
> const int ArgumentReg1 = 5;
> const int ArgumentReg2 = 6;
> const int ArgumentReg3 = 7;
87a198,200
> const int ArgumentReg[] = {4, 5, 6, 7};
> const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
>
90c203
< const int SyscallSuccessReg = ArgumentReg[3];
---
> const int SyscallSuccessReg = ArgumentReg3;
104a218,221
> // These help enumerate all the registers for dependence tracking.
> const int FP_Base_DepTag = NumIntRegs;
> const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
>
113c230
< Index = 0, //Bank 0: 0 - 3
---
> Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3
118c235
< Random = 8, //Bank 1: 8 - 15
---
> CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15
127c244
< EntryLo0 = 16, //Bank 2: 16 - 23
---
> EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23
136c253
< EntryLo1 = 24, // Bank 3: 24
---
> EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24
138c255
< Context = 32, // Bank 4: 32 - 33
---
> Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33
141,142c258,259
< //PageMask = 40, //Bank 5: 40 - 41
< PageGrain = 41,
---
> PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
> PageGrain = Ctrl_Base_DepTag + 41,
144c261
< Wired = 48, //Bank 6:48-55
---
> Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55
151c268
< HWRena = 56, //Bank 7: 56-63
---
> HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63
153c270
< BadVAddr = 64, //Bank 8: 64-71
---
> BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71
155c272
< Count = 72, //Bank 9: 72-79
---
> Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79
157c274
< EntryHi = 80, //Bank 10: 80-87
---
> EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87
159c276
< Compare = 88, //Bank 11: 88-95
---
> Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95
161c278
< Status = 96, //Bank 12: 96-103
---
> Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103
166c283
< Cause = 104, //Bank 13: 104-111
---
> Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111
168c285
< EPC = 112, //Bank 14: 112-119
---
> EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119
170c287
< PRId = 120, //Bank 15: 120-127,
---
> PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127,
173c290
< Config = 128, //Bank 16: 128-135
---
> Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135
183c300
< LLAddr = 136, //Bank 17: 136-143
---
> LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143
185c302
< WatchLo0 = 144, //Bank 18: 144-151
---
> WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151
194c311
< WatchHi0 = 152, //Bank 19: 152-159
---
> WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159
203c320
< XCContext64 = 160, //Bank 20: 160-167
---
> XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
209c326
< Debug = 184, //Bank 23: 184-191
---
> Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191
215c332
< DEPC = 192, //Bank 24: 192-199
---
> DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199
217c334
< PerfCnt0 = 200, //Bank 25: 200-207
---
> PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207
226c343
< ErrCtl = 208, //Bank 26: 208-215
---
> ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215
228c345
< CacheErr0 = 216, //Bank 27: 216-223
---
> CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223
233c350
< TagLo0 = 224, //Bank 28: 224-231
---
> TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231
242c359
< TagHi0 = 232, //Bank 29: 232-239
---
> TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239
252c369
< ErrorEPC = 240, //Bank 30: 240-247
---
> ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247
254c371
< DESAVE = 248, //Bank 31: 248-256
---
> DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256
256c373
< LLFlag = 257,
---
> LLFlag = Ctrl_Base_DepTag + 257,
261,262c378,379
< const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
< const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
---
> const int TotalDataRegs = NumIntRegs + NumFloatRegs;
>
267d383
< const int TotalDataRegs = NumIntRegs + NumFloatRegs;
269,271d384
< // These help enumerate all the registers for dependence tracking.
< const int FP_Base_DepTag = NumIntRegs;
< const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;