isa_traits.hh (2680:246e7104f744) | isa_traits.hh (2754:e3d023bc752c) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 * Korey Sewell 30 */ 31 32#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 33#define __ARCH_MIPS_ISA_TRAITS_HH__ 34 35#include "arch/mips/constants.hh" 36#include "arch/mips/types.hh" 37#include "arch/mips/regfile/regfile.hh" 38#include "arch/mips/faults.hh" 39#include "arch/mips/utility.hh" 40#include "base/misc.hh" 41#include "config/full_system.hh" 42#include "sim/byteswap.hh" 43#include "sim/host.hh" 44#include "sim/faults.hh" 45 46#include <vector> 47 48class FastCPU; 49class FullCPU; 50class Checkpoint; 51class ThreadContext; 52 53namespace LittleEndianGuest {}; 54 55#define TARGET_MIPS 56 57class StaticInst; 58class StaticInstPtr; 59 | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 * Korey Sewell 30 */ 31 32#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 33#define __ARCH_MIPS_ISA_TRAITS_HH__ 34 35#include "arch/mips/constants.hh" 36#include "arch/mips/types.hh" 37#include "arch/mips/regfile/regfile.hh" 38#include "arch/mips/faults.hh" 39#include "arch/mips/utility.hh" 40#include "base/misc.hh" 41#include "config/full_system.hh" 42#include "sim/byteswap.hh" 43#include "sim/host.hh" 44#include "sim/faults.hh" 45 46#include <vector> 47 48class FastCPU; 49class FullCPU; 50class Checkpoint; 51class ThreadContext; 52 53namespace LittleEndianGuest {}; 54 55#define TARGET_MIPS 56 57class StaticInst; 58class StaticInstPtr; 59 |
60namespace MIPS34K { 61int DTB_ASN_ASN(uint64_t reg); 62int ITB_ASN_ASN(uint64_t reg); 63}; 64 65#if !FULL_SYSTEM | |
66class SyscallReturn { 67 public: 68 template <class T> 69 SyscallReturn(T v, bool s) 70 { 71 retval = (uint32_t)v; 72 success = s; 73 } 74 75 template <class T> 76 SyscallReturn(T v) 77 { 78 success = (v >= 0); 79 retval = (uint32_t)v; 80 } 81 82 ~SyscallReturn() {} 83 84 SyscallReturn& operator=(const SyscallReturn& s) { 85 retval = s.retval; 86 success = s.success; 87 return *this; 88 } 89 90 bool successful() { return success; } 91 uint64_t value() { return retval; } 92 93 94 private: 95 uint64_t retval; 96 bool success; 97}; | 60class SyscallReturn { 61 public: 62 template <class T> 63 SyscallReturn(T v, bool s) 64 { 65 retval = (uint32_t)v; 66 success = s; 67 } 68 69 template <class T> 70 SyscallReturn(T v) 71 { 72 success = (v >= 0); 73 retval = (uint32_t)v; 74 } 75 76 ~SyscallReturn() {} 77 78 SyscallReturn& operator=(const SyscallReturn& s) { 79 retval = s.retval; 80 success = s.success; 81 return *this; 82 } 83 84 bool successful() { return success; } 85 uint64_t value() { return retval; } 86 87 88 private: 89 uint64_t retval; 90 bool success; 91}; |
98#endif | |
99 100namespace MipsISA 101{ 102 using namespace LittleEndianGuest; 103 104 static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) 105 { 106 if (return_value.successful()) { 107 // no error 108 regs->setIntReg(SyscallSuccessReg, 0); 109 regs->setIntReg(ReturnValueReg1, return_value.value()); 110 } else { 111 // got an error, return details 112 regs->setIntReg(SyscallSuccessReg, (IntReg) -1); 113 regs->setIntReg(ReturnValueReg1, -return_value.value()); 114 } 115 } 116 117 StaticInstPtr decodeInst(ExtMachInst); 118 119 static inline ExtMachInst 120 makeExtMI(MachInst inst, const uint64_t &pc) { 121#if FULL_SYSTEM 122 ExtMachInst ext_inst = inst; 123 if (pc && 0x1) 124 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); 125 else 126 return ext_inst; 127#else 128 return ExtMachInst(inst); 129#endif 130 } 131 132 /** 133 * Function to insure ISA semantics about 0 registers. 134 * @param tc The thread context. 135 */ 136 template <class TC> 137 void zeroRegisters(TC *tc); 138 139 const Addr MaxAddr = (Addr)-1; 140 141 void copyRegs(ThreadContext *src, ThreadContext *dest); 142 | 92 93namespace MipsISA 94{ 95 using namespace LittleEndianGuest; 96 97 static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) 98 { 99 if (return_value.successful()) { 100 // no error 101 regs->setIntReg(SyscallSuccessReg, 0); 102 regs->setIntReg(ReturnValueReg1, return_value.value()); 103 } else { 104 // got an error, return details 105 regs->setIntReg(SyscallSuccessReg, (IntReg) -1); 106 regs->setIntReg(ReturnValueReg1, -return_value.value()); 107 } 108 } 109 110 StaticInstPtr decodeInst(ExtMachInst); 111 112 static inline ExtMachInst 113 makeExtMI(MachInst inst, const uint64_t &pc) { 114#if FULL_SYSTEM 115 ExtMachInst ext_inst = inst; 116 if (pc && 0x1) 117 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); 118 else 119 return ext_inst; 120#else 121 return ExtMachInst(inst); 122#endif 123 } 124 125 /** 126 * Function to insure ISA semantics about 0 registers. 127 * @param tc The thread context. 128 */ 129 template <class TC> 130 void zeroRegisters(TC *tc); 131 132 const Addr MaxAddr = (Addr)-1; 133 134 void copyRegs(ThreadContext *src, ThreadContext *dest); 135 |
143 uint64_t fpConvert(double fp_val, ConvertType cvt_type); 144 double roundFP(double val, int digits); 145 double truncFP(double val); 146 bool getFPConditionCode(uint32_t fcsr_reg, int cc); 147 uint32_t makeCCVector(uint32_t fcsr, int num, bool val); 148 | |
149 // Machine operations 150 151 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 152 int regnum); 153 154 void restoreMachineReg(RegFile ®s, const AnyReg ®, 155 int regnum); 156 157#if 0 158 static void serializeSpecialRegs(const Serializable::Proxy &proxy, 159 const RegFile ®s); 160 161 static void unserializeSpecialRegs(const IniFile *db, 162 const std::string &category, 163 ConfigNode *node, 164 RegFile ®s); 165#endif 166 167 static inline Addr alignAddress(const Addr &addr, 168 unsigned int nbytes) { 169 return (addr & ~(nbytes - 1)); 170 } 171 172 // Instruction address compression hooks 173 static inline Addr realPCToFetchPC(const Addr &addr) { 174 return addr; 175 } 176 177 static inline Addr fetchPCToRealPC(const Addr &addr) { 178 return addr; 179 } 180 181 // the size of "fetched" instructions (not necessarily the size 182 // of real instructions for PISA) 183 static inline size_t fetchInstSize() { 184 return sizeof(MachInst); 185 } 186 187 static inline MachInst makeRegisterCopy(int dest, int src) { 188 panic("makeRegisterCopy not implemented"); 189 return 0; 190 } 191 192}; 193 | 136 // Machine operations 137 138 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 139 int regnum); 140 141 void restoreMachineReg(RegFile ®s, const AnyReg ®, 142 int regnum); 143 144#if 0 145 static void serializeSpecialRegs(const Serializable::Proxy &proxy, 146 const RegFile ®s); 147 148 static void unserializeSpecialRegs(const IniFile *db, 149 const std::string &category, 150 ConfigNode *node, 151 RegFile ®s); 152#endif 153 154 static inline Addr alignAddress(const Addr &addr, 155 unsigned int nbytes) { 156 return (addr & ~(nbytes - 1)); 157 } 158 159 // Instruction address compression hooks 160 static inline Addr realPCToFetchPC(const Addr &addr) { 161 return addr; 162 } 163 164 static inline Addr fetchPCToRealPC(const Addr &addr) { 165 return addr; 166 } 167 168 // the size of "fetched" instructions (not necessarily the size 169 // of real instructions for PISA) 170 static inline size_t fetchInstSize() { 171 return sizeof(MachInst); 172 } 173 174 static inline MachInst makeRegisterCopy(int dest, int src) { 175 panic("makeRegisterCopy not implemented"); 176 return 0; 177 } 178 179}; 180 |
194#if FULL_SYSTEM 195 196#include "arch/mips/mips34k.hh" 197 198#endif 199 | |
200using namespace MipsISA; 201 202#endif // __ARCH_MIPS_ISA_TRAITS_HH__ | 181using namespace MipsISA; 182 183#endif // __ARCH_MIPS_ISA_TRAITS_HH__ |