utility.hh (9180:ee8d7a51651d) utility.hh (10037:5cac77888310)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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49#include "arch/arm/miscregs.hh"
50#include "arch/arm/types.hh"
51#include "base/misc.hh"
52#include "base/trace.hh"
53#include "base/types.hh"
54#include "cpu/static_inst.hh"
55#include "cpu/thread_context.hh"
56
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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49#include "arch/arm/miscregs.hh"
50#include "arch/arm/types.hh"
51#include "base/misc.hh"
52#include "base/trace.hh"
53#include "base/types.hh"
54#include "cpu/static_inst.hh"
55#include "cpu/thread_context.hh"
56
57class ArmSystem;
58
57namespace ArmISA {
58
59inline PCState
60buildRetPC(const PCState &curPC, const PCState &callPC)
61{
62 PCState retPC = callPC;
63 retPC.uEnd();
64 return retPC;

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113 panic("Copy Misc. Regs Not Implemented Yet\n");
114}
115
116void initCPU(ThreadContext *tc, int cpuId);
117
118static inline bool
119inUserMode(CPSR cpsr)
120{
59namespace ArmISA {
60
61inline PCState
62buildRetPC(const PCState &curPC, const PCState &callPC)
63{
64 PCState retPC = callPC;
65 retPC.uEnd();
66 return retPC;

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115 panic("Copy Misc. Regs Not Implemented Yet\n");
116}
117
118void initCPU(ThreadContext *tc, int cpuId);
119
120static inline bool
121inUserMode(CPSR cpsr)
122{
121 return cpsr.mode == MODE_USER;
123 return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
122}
123
124static inline bool
125inUserMode(ThreadContext *tc)
126{
127 return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
128}
129

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134}
135
136static inline bool
137inPrivilegedMode(ThreadContext *tc)
138{
139 return !inUserMode(tc);
140}
141
124}
125
126static inline bool
127inUserMode(ThreadContext *tc)
128{
129 return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
130}
131

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136}
137
138static inline bool
139inPrivilegedMode(ThreadContext *tc)
140{
141 return !inUserMode(tc);
142}
143
142static inline bool
143vfpEnabled(CPACR cpacr, CPSR cpsr)
144bool inAArch64(ThreadContext *tc);
145
146static inline OperatingMode
147currOpMode(ThreadContext *tc)
144{
148{
145 return cpacr.cp10 == 0x3 ||
146 (cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr));
149 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
150 return (OperatingMode) (uint8_t) cpsr.mode;
147}
148
151}
152
153static inline ExceptionLevel
154currEL(ThreadContext *tc)
155{
156 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
157 return (ExceptionLevel) (uint8_t) cpsr.el;
158}
159
160bool ELIs64(ThreadContext *tc, ExceptionLevel el);
161
162bool isBigEndian64(ThreadContext *tc);
163
164/**
165 * Removes the tag from tagged addresses if that mode is enabled.
166 * @param addr The address to be purified.
167 * @param tc The thread context.
168 * @param el The controlled exception level.
169 * @return The purified address.
170 */
171Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el);
172
149static inline bool
173static inline bool
150vfpEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
174inSecureState(SCR scr, CPSR cpsr)
151{
175{
152 if ((cpacr.cp11 == 0x3) ||
153 ((cpacr.cp11 == 0x1) && inPrivilegedMode(cpsr)))
154 return fpexc.en && vfpEnabled(cpacr, cpsr);
155 else
156 return fpexc.en && vfpEnabled(cpacr, cpsr) &&
157 (cpacr.cp11 == cpacr.cp10);
176 switch ((OperatingMode) (uint8_t) cpsr.mode) {
177 case MODE_MON:
178 case MODE_EL3T:
179 case MODE_EL3H:
180 return true;
181 case MODE_HYP:
182 case MODE_EL2T:
183 case MODE_EL2H:
184 return false;
185 default:
186 return !scr.ns;
187 }
158}
159
188}
189
190bool longDescFormatInUse(ThreadContext *tc);
191
192bool inSecureState(ThreadContext *tc);
193
194uint32_t getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
195
196static inline uint32_t
197mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
198 uint32_t opc1, uint32_t opc2)
199{
200 return (isRead << 0) |
201 (crm << 1) |
202 (rt << 5) |
203 (crn << 10) |
204 (opc1 << 14) |
205 (opc2 << 17);
206}
207
208static inline void
209mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt,
210 uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
211{
212 isRead = (iss >> 0) & 0x1;
213 crm = (iss >> 1) & 0xF;
214 rt = (IntRegIndex) ((iss >> 5) & 0xF);
215 crn = (iss >> 10) & 0xF;
216 opc1 = (iss >> 14) & 0x7;
217 opc2 = (iss >> 17) & 0x7;
218}
219
220static inline uint32_t
221mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2,
222 uint32_t opc1)
223{
224 return (isRead << 0) |
225 (crm << 1) |
226 (rt << 5) |
227 (rt2 << 10) |
228 (opc1 << 16);
229}
230
231static inline uint32_t
232msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn,
233 uint32_t crm, uint32_t op2, IntRegIndex rt)
234{
235 return isRead |
236 (crm << 1) |
237 (rt << 5) |
238 (crn << 10) |
239 (op1 << 14) |
240 (op2 << 17) |
241 (op0 << 20);
242}
243
244bool
245mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
246 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
247bool
248mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
249 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
250bool
251mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
252 HCR hcr, uint32_t iss);
253
254bool msrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el,
255 CPACR cpacr);
256bool msrMrs64TrapToHyp(const MiscRegIndex miscReg, bool isRead, CPTR cptr,
257 HCR hcr, bool * isVfpNeon);
258bool msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr,
259 ExceptionLevel el, bool * isVfpNeon);
260
261bool
262vfpNeonEnabled(uint32_t &seq, HCPTR hcptr, NSACR nsacr, CPACR cpacr, CPSR cpsr,
263 uint32_t &iss, bool &trap, ThreadContext *tc,
264 FPEXC fpexc = (1<<30), bool isSIMD = false);
265
160static inline bool
266static inline bool
161neonEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
267vfpNeon64Enabled(CPACR cpacr, ExceptionLevel el)
162{
268{
163 return !cpacr.asedis && vfpEnabled(cpacr, cpsr, fpexc);
269 if ((el == EL0 && cpacr.fpen != 0x3) ||
270 (el == EL1 && !(cpacr.fpen & 0x1)))
271 return false;
272 return true;
164}
165
273}
274
275bool SPAlignmentCheckEnabled(ThreadContext* tc);
276
166uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
167
168void skipFunction(ThreadContext *tc);
169
170inline void
171advancePC(PCState &pc, const StaticInstPtr inst)
172{
173 inst->advancePC(pc);
174}
175
176Addr truncPage(Addr addr);
177Addr roundPage(Addr addr);
178
179inline uint64_t
180getExecutingAsid(ThreadContext *tc)
181{
182 return tc->readMiscReg(MISCREG_CONTEXTIDR);
183}
184
277uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
278
279void skipFunction(ThreadContext *tc);
280
281inline void
282advancePC(PCState &pc, const StaticInstPtr inst)
283{
284 inst->advancePC(pc);
285}
286
287Addr truncPage(Addr addr);
288Addr roundPage(Addr addr);
289
290inline uint64_t
291getExecutingAsid(ThreadContext *tc)
292{
293 return tc->readMiscReg(MISCREG_CONTEXTIDR);
294}
295
296// Decodes the register index to access based on the fields used in a MSR
297// or MRS instruction
298bool
299decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
300 CPSR cpsr, SCR scr, NSACR nsacr,
301 bool checkSecurity = true);
302
303// This wrapper function is used to turn the register index into a source
304// parameter for the instruction. See Operands.isa
305static inline int
306decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
307{
308 int regIdx;
309 bool isIntReg;
310 bool validReg;
311
312 validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0, false);
313 return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
185}
186
314}
315
316/**
317 * Returns the n. of PA bits corresponding to the specified encoding.
318 */
319int decodePhysAddrRange64(uint8_t pa_enc);
320
321/**
322 * Returns the encoding corresponding to the specified n. of PA bits.
323 */
324uint8_t encodePhysAddrRange64(int pa_size);
325
326}
327
187#endif
328#endif