utility.hh (7707:e5b6f1157be3) utility.hh (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46#define __ARCH_ARM_UTILITY_HH__
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/miscregs.hh"
50#include "arch/arm/types.hh"
51#include "base/misc.hh"
52#include "base/trace.hh"
53#include "base/types.hh"
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46#define __ARCH_ARM_UTILITY_HH__
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/miscregs.hh"
50#include "arch/arm/types.hh"
51#include "base/misc.hh"
52#include "base/trace.hh"
53#include "base/types.hh"
54#include "cpu/static_inst.hh"
54#include "cpu/thread_context.hh"
55
56namespace ArmISA {
57
55#include "cpu/thread_context.hh"
56
57namespace ArmISA {
58
59 inline PCState
60 buildRetPC(const PCState &curPC, const PCState &callPC)
61 {
62 PCState retPC = callPC;
63 retPC.uEnd();
64 return retPC;
65 }
66
58 inline bool
59 testPredicate(CPSR cpsr, ConditionCode code)
60 {
61 switch (code)
62 {
63 case COND_EQ: return cpsr.z;
64 case COND_NE: return !cpsr.z;
65 case COND_CS: return cpsr.c;

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88 template <class TC>
89 void zeroRegisters(TC *tc);
90
91 inline void startupCPU(ThreadContext *tc, int cpuId)
92 {
93 tc->activate(0);
94 }
95
67 inline bool
68 testPredicate(CPSR cpsr, ConditionCode code)
69 {
70 switch (code)
71 {
72 case COND_EQ: return cpsr.z;
73 case COND_NE: return !cpsr.z;
74 case COND_CS: return cpsr.c;

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97 template <class TC>
98 void zeroRegisters(TC *tc);
99
100 inline void startupCPU(ThreadContext *tc, int cpuId)
101 {
102 tc->activate(0);
103 }
104
96 static inline bool
97 isThumb(Addr pc)
98 {
99 return (pc & PcTBit);
100 }
101
102 static inline void
103 copyRegs(ThreadContext *src, ThreadContext *dest)
104 {
105 panic("Copy Regs Not Implemented Yet\n");
106 }
107
108 static inline void
109 copyMiscRegs(ThreadContext *src, ThreadContext *dest)

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158
159uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
160
161Fault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
162Fault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
163
164void skipFunction(ThreadContext *tc);
165
105 static inline void
106 copyRegs(ThreadContext *src, ThreadContext *dest)
107 {
108 panic("Copy Regs Not Implemented Yet\n");
109 }
110
111 static inline void
112 copyMiscRegs(ThreadContext *src, ThreadContext *dest)

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161
162uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
163
164Fault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
165Fault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
166
167void skipFunction(ThreadContext *tc);
168
169inline void
170advancePC(PCState &pc, const StaticInstPtr inst)
171{
172 inst->advancePC(pc);
173}
174
166};
167
168
169#endif
175};
176
177
178#endif