utility.hh (6242:1cee707c1228) | utility.hh (6246:5744fafb5072) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007-2008 The Florida State University 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 21 unchanged lines hidden (view full) --- 30 * Stephen Hines 31 */ 32 33#ifndef __ARCH_ARM_UTILITY_HH__ 34#define __ARCH_ARM_UTILITY_HH__ 35 36#include "arch/arm/miscregs.hh" 37#include "arch/arm/types.hh" | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007-2008 The Florida State University 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 21 unchanged lines hidden (view full) --- 30 * Stephen Hines 31 */ 32 33#ifndef __ARCH_ARM_UTILITY_HH__ 34#define __ARCH_ARM_UTILITY_HH__ 35 36#include "arch/arm/miscregs.hh" 37#include "arch/arm/types.hh" |
38#include "base/misc.hh" | |
39#include "base/types.hh" | 38#include "base/types.hh" |
40#include "config/full_system.hh" | |
41#include "cpu/thread_context.hh" 42 | 39#include "cpu/thread_context.hh" 40 |
43class ThreadContext; 44 | |
45namespace ArmISA { 46 47 inline bool 48 testPredicate(CPSR cpsr, ConditionCode code) 49 { 50 switch (code) 51 { 52 case COND_EQ: return cpsr.z; --- 12 unchanged lines hidden (view full) --- 65 case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z); 66 case COND_AL: return true; 67 case COND_NV: return false; 68 default: 69 panic("Unhandled predicate condition: %d\n", code); 70 } 71 } 72 | 41namespace ArmISA { 42 43 inline bool 44 testPredicate(CPSR cpsr, ConditionCode code) 45 { 46 switch (code) 47 { 48 case COND_EQ: return cpsr.z; --- 12 unchanged lines hidden (view full) --- 61 case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z); 62 case COND_AL: return true; 63 case COND_NV: return false; 64 default: 65 panic("Unhandled predicate condition: %d\n", code); 66 } 67 } 68 |
73 //Floating Point Utility Functions 74 uint64_t fpConvert(ConvertType cvt_type, double fp_val); 75 double roundFP(double val, int digits); 76 double truncFP(double val); 77 78 bool getCondCode(uint32_t fcsr, int cc); 79 uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 80 uint32_t genInvalidVector(uint32_t fcsr); 81 82 bool isNan(void *val_ptr, int size); 83 bool isQnan(void *val_ptr, int size); 84 bool isSnan(void *val_ptr, int size); 85 | |
86 /** 87 * Function to insure ISA semantics about 0 registers. 88 * @param tc The thread context. 89 */ 90 template <class TC> 91 void zeroRegisters(TC *tc); 92 93 // Instruction address compression hooks --- 14 unchanged lines hidden (view full) --- 108 panic("makeRegisterCopy not implemented"); 109 return 0; 110 } 111 112 inline void startupCPU(ThreadContext *tc, int cpuId) 113 { 114 tc->activate(0); 115 } | 69 /** 70 * Function to insure ISA semantics about 0 registers. 71 * @param tc The thread context. 72 */ 73 template <class TC> 74 void zeroRegisters(TC *tc); 75 76 // Instruction address compression hooks --- 14 unchanged lines hidden (view full) --- 91 panic("makeRegisterCopy not implemented"); 92 return 0; 93 } 94 95 inline void startupCPU(ThreadContext *tc, int cpuId) 96 { 97 tc->activate(0); 98 } |
99 100 template <class XC> 101 Fault 102 checkFpEnableFault(XC *xc) 103 { 104 return NoFault; 105 } |
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116}; 117 118 119#endif | 106}; 107 108 109#endif |