1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Korey Sewell 42 * Stephen Hines 43 */ 44 45#ifndef __ARCH_ARM_UTILITY_HH__ 46#define __ARCH_ARM_UTILITY_HH__ 47 48#include "arch/arm/isa_traits.hh" 49#include "arch/arm/miscregs.hh" 50#include "arch/arm/types.hh" 51#include "base/misc.hh" 52#include "base/trace.hh" 53#include "base/types.hh" 54#include "cpu/static_inst.hh" 55#include "cpu/thread_context.hh" 56 57namespace ArmISA { 58
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59 inline PCState
60 buildRetPC(const PCState &curPC, const PCState &callPC)
61 {
62 PCState retPC = callPC;
63 retPC.uEnd();
64 return retPC;
65 }
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59inline PCState 60buildRetPC(const PCState &curPC, const PCState &callPC) 61{ 62 PCState retPC = callPC; 63 retPC.uEnd(); 64 return retPC; 65} |
66
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67 inline bool
68 testPredicate(CPSR cpsr, ConditionCode code)
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67inline bool 68testPredicate(CPSR cpsr, ConditionCode code) 69{ 70 switch (code) |
71 {
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70 switch (code)
71 {
72 case COND_EQ: return cpsr.z;
73 case COND_NE: return !cpsr.z;
74 case COND_CS: return cpsr.c;
75 case COND_CC: return !cpsr.c;
76 case COND_MI: return cpsr.n;
77 case COND_PL: return !cpsr.n;
78 case COND_VS: return cpsr.v;
79 case COND_VC: return !cpsr.v;
80 case COND_HI: return (cpsr.c && !cpsr.z);
81 case COND_LS: return !(cpsr.c && !cpsr.z);
82 case COND_GE: return !(cpsr.n ^ cpsr.v);
83 case COND_LT: return (cpsr.n ^ cpsr.v);
84 case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z);
85 case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z);
86 case COND_AL: return true;
87 case COND_UC: return true;
88 default:
89 panic("Unhandled predicate condition: %d\n", code);
90 }
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72 case COND_EQ: return cpsr.z; 73 case COND_NE: return !cpsr.z; 74 case COND_CS: return cpsr.c; 75 case COND_CC: return !cpsr.c; 76 case COND_MI: return cpsr.n; 77 case COND_PL: return !cpsr.n; 78 case COND_VS: return cpsr.v; 79 case COND_VC: return !cpsr.v; 80 case COND_HI: return (cpsr.c && !cpsr.z); 81 case COND_LS: return !(cpsr.c && !cpsr.z); 82 case COND_GE: return !(cpsr.n ^ cpsr.v); 83 case COND_LT: return (cpsr.n ^ cpsr.v); 84 case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z); 85 case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z); 86 case COND_AL: return true; 87 case COND_UC: return true; 88 default: 89 panic("Unhandled predicate condition: %d\n", code); |
90 }
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91} |
92
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93 /**
94 * Function to insure ISA semantics about 0 registers.
95 * @param tc The thread context.
96 */
97 template <class TC>
98 void zeroRegisters(TC *tc);
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93/** 94 * Function to insure ISA semantics about 0 registers. 95 * @param tc The thread context. 96 */ 97template 98void zeroRegisters(TC *tc); |
99
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100 inline void startupCPU(ThreadContext *tc, int cpuId)
101 {
102 tc->activate(0);
103 }
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100inline void startupCPU(ThreadContext *tc, int cpuId) 101{ 102 tc->activate(0); 103} |
104
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105 void copyRegs(ThreadContext *src, ThreadContext *dest);
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105void copyRegs(ThreadContext *src, ThreadContext *dest); |
106
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107 static inline void
108 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
109 {
110 panic("Copy Misc. Regs Not Implemented Yet\n");
111 }
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107static inline void 108copyMiscRegs(ThreadContext *src, ThreadContext *dest) 109{ 110 panic("Copy Misc. Regs Not Implemented Yet\n"); 111} |
112
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113 void initCPU(ThreadContext *tc, int cpuId);
114
115 static inline bool
116 inUserMode(CPSR cpsr)
117 {
118 return cpsr.mode == MODE_USER;
119 }
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113void initCPU(ThreadContext *tc, int cpuId); |
114
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121 static inline bool
122 inUserMode(ThreadContext *tc)
123 {
124 return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
125 }
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115static inline bool 116inUserMode(CPSR cpsr) 117{ 118 return cpsr.mode == MODE_USER; 119} |
120
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127 static inline bool
128 inPrivilegedMode(CPSR cpsr)
129 {
130 return !inUserMode(cpsr);
131 }
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121static inline bool 122inUserMode(ThreadContext *tc) 123{ 124 return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR)); 125} |
126
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133 static inline bool
134 inPrivilegedMode(ThreadContext *tc)
135 {
136 return !inUserMode(tc);
137 }
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127static inline bool 128inPrivilegedMode(CPSR cpsr) 129{ 130 return !inUserMode(cpsr); 131} |
132
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139 static inline bool
140 vfpEnabled(CPACR cpacr, CPSR cpsr)
141 {
142 return cpacr.cp10 == 0x3 ||
143 (cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr));
144 }
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133static inline bool 134inPrivilegedMode(ThreadContext *tc) 135{ 136 return !inUserMode(tc); 137} |
138
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146 static inline bool
147 vfpEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
148 {
149 return fpexc.en && vfpEnabled(cpacr, cpsr);
150 }
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139static inline bool 140vfpEnabled(CPACR cpacr, CPSR cpsr) 141{ 142 return cpacr.cp10 == 0x3 || 143 (cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr)); 144} |
145
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152 static inline bool
153 neonEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
154 {
155 return !cpacr.asedis && vfpEnabled(cpacr, cpsr, fpexc);
156 }
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146static inline bool 147vfpEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc) 148{ 149 return fpexc.en && vfpEnabled(cpacr, cpsr); 150} |
151
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152static inline bool 153neonEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc) 154{ 155 return !cpacr.asedis && vfpEnabled(cpacr, cpsr, fpexc); 156} 157 |
158uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 159 160Fault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2); 161Fault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2); 162 163void skipFunction(ThreadContext *tc); 164 165inline void 166advancePC(PCState &pc, const StaticInstPtr inst) 167{ 168 inst->advancePC(pc); 169} 170 171}; 172 173 174#endif
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