1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007-2008 The Florida State University 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 21 unchanged lines hidden (view full) --- 30 * Stephen Hines 31 */ 32 33#ifndef __ARCH_ARM_UTILITY_HH__ 34#define __ARCH_ARM_UTILITY_HH__ 35 36#include "arch/arm/miscregs.hh" 37#include "arch/arm/types.hh" |
38#include "base/types.hh" |
39#include "cpu/thread_context.hh" 40 |
41namespace ArmISA { 42 43 inline bool 44 testPredicate(CPSR cpsr, ConditionCode code) 45 { 46 switch (code) 47 { 48 case COND_EQ: return cpsr.z; --- 12 unchanged lines hidden (view full) --- 61 case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z); 62 case COND_AL: return true; 63 case COND_NV: return false; 64 default: 65 panic("Unhandled predicate condition: %d\n", code); 66 } 67 } 68 |
69 /** 70 * Function to insure ISA semantics about 0 registers. 71 * @param tc The thread context. 72 */ 73 template <class TC> 74 void zeroRegisters(TC *tc); 75 76 // Instruction address compression hooks --- 14 unchanged lines hidden (view full) --- 91 panic("makeRegisterCopy not implemented"); 92 return 0; 93 } 94 95 inline void startupCPU(ThreadContext *tc, int cpuId) 96 { 97 tc->activate(0); 98 } |
99 100 template <class XC> 101 Fault 102 checkFpEnableFault(XC *xc) 103 { 104 return NoFault; 105 } |
106}; 107 108 109#endif |