1/* 2 * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 143 unchanged lines hidden (view full) --- 152 153static inline ExceptionLevel 154currEL(ThreadContext *tc) 155{ 156 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 157 return (ExceptionLevel) (uint8_t) cpsr.el; 158} 159 |
160/** 161 * This function checks whether selected EL provided as an argument 162 * is using the AArch32 ISA. This information might be unavailable 163 * at the current EL status: it hence returns a pair of boolean values: 164 * a first boolean, true if information is available (known), 165 * and a second one, true if EL is using AArch32, false for AArch64. 166 * 167 * @param tc The thread context. 168 * @param el The target exception level. 169 * @retval known is FALSE for EL0 if the current Exception level 170 * is not EL0 and EL1 is using AArch64, since it cannot 171 * determine the state of EL0; TRUE otherwise. 172 * @retval aarch32 is TRUE if the specified Exception level is using AArch32; 173 * FALSE otherwise. 174 */ 175std::pair<bool, bool> 176ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el); 177 |
178bool ELIs32(ThreadContext *tc, ExceptionLevel el); 179 180bool ELIs64(ThreadContext *tc, ExceptionLevel el); 181 182bool isBigEndian64(ThreadContext *tc); 183 184static inline uint8_t 185itState(CPSR psr) --- 168 unchanged lines hidden --- |