1/*
| 1/*
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2 * Copyright (c) 2010 ARM Limited
| 2 * Copyright (c) 2010, 2012-2013 ARM Limited
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3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Korey Sewell 42 * Stephen Hines 43 */ 44 45#ifndef __ARCH_ARM_UTILITY_HH__ 46#define __ARCH_ARM_UTILITY_HH__ 47 48#include "arch/arm/isa_traits.hh" 49#include "arch/arm/miscregs.hh" 50#include "arch/arm/types.hh" 51#include "base/misc.hh" 52#include "base/trace.hh" 53#include "base/types.hh" 54#include "cpu/static_inst.hh" 55#include "cpu/thread_context.hh" 56
| 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Korey Sewell 42 * Stephen Hines 43 */ 44 45#ifndef __ARCH_ARM_UTILITY_HH__ 46#define __ARCH_ARM_UTILITY_HH__ 47 48#include "arch/arm/isa_traits.hh" 49#include "arch/arm/miscregs.hh" 50#include "arch/arm/types.hh" 51#include "base/misc.hh" 52#include "base/trace.hh" 53#include "base/types.hh" 54#include "cpu/static_inst.hh" 55#include "cpu/thread_context.hh" 56
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| 57class ArmSystem; 58
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57namespace ArmISA { 58 59inline PCState 60buildRetPC(const PCState &curPC, const PCState &callPC) 61{ 62 PCState retPC = callPC; 63 retPC.uEnd(); 64 return retPC; 65} 66 67inline bool 68testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code) 69{ 70 bool n = (nz & 0x2); 71 bool z = (nz & 0x1); 72 73 switch (code) 74 { 75 case COND_EQ: return z; 76 case COND_NE: return !z; 77 case COND_CS: return c; 78 case COND_CC: return !c; 79 case COND_MI: return n; 80 case COND_PL: return !n; 81 case COND_VS: return v; 82 case COND_VC: return !v; 83 case COND_HI: return (c && !z); 84 case COND_LS: return !(c && !z); 85 case COND_GE: return !(n ^ v); 86 case COND_LT: return (n ^ v); 87 case COND_GT: return !(n ^ v || z); 88 case COND_LE: return (n ^ v || z); 89 case COND_AL: return true; 90 case COND_UC: return true; 91 default: 92 panic("Unhandled predicate condition: %d\n", code); 93 } 94} 95 96/** 97 * Function to insure ISA semantics about 0 registers. 98 * @param tc The thread context. 99 */ 100template <class TC> 101void zeroRegisters(TC *tc); 102 103inline void startupCPU(ThreadContext *tc, int cpuId) 104{ 105 tc->activate(Cycles(0)); 106} 107 108void copyRegs(ThreadContext *src, ThreadContext *dest); 109 110static inline void 111copyMiscRegs(ThreadContext *src, ThreadContext *dest) 112{ 113 panic("Copy Misc. Regs Not Implemented Yet\n"); 114} 115 116void initCPU(ThreadContext *tc, int cpuId); 117 118static inline bool 119inUserMode(CPSR cpsr) 120{
| 59namespace ArmISA { 60 61inline PCState 62buildRetPC(const PCState &curPC, const PCState &callPC) 63{ 64 PCState retPC = callPC; 65 retPC.uEnd(); 66 return retPC; 67} 68 69inline bool 70testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code) 71{ 72 bool n = (nz & 0x2); 73 bool z = (nz & 0x1); 74 75 switch (code) 76 { 77 case COND_EQ: return z; 78 case COND_NE: return !z; 79 case COND_CS: return c; 80 case COND_CC: return !c; 81 case COND_MI: return n; 82 case COND_PL: return !n; 83 case COND_VS: return v; 84 case COND_VC: return !v; 85 case COND_HI: return (c && !z); 86 case COND_LS: return !(c && !z); 87 case COND_GE: return !(n ^ v); 88 case COND_LT: return (n ^ v); 89 case COND_GT: return !(n ^ v || z); 90 case COND_LE: return (n ^ v || z); 91 case COND_AL: return true; 92 case COND_UC: return true; 93 default: 94 panic("Unhandled predicate condition: %d\n", code); 95 } 96} 97 98/** 99 * Function to insure ISA semantics about 0 registers. 100 * @param tc The thread context. 101 */ 102template <class TC> 103void zeroRegisters(TC *tc); 104 105inline void startupCPU(ThreadContext *tc, int cpuId) 106{ 107 tc->activate(Cycles(0)); 108} 109 110void copyRegs(ThreadContext *src, ThreadContext *dest); 111 112static inline void 113copyMiscRegs(ThreadContext *src, ThreadContext *dest) 114{ 115 panic("Copy Misc. Regs Not Implemented Yet\n"); 116} 117 118void initCPU(ThreadContext *tc, int cpuId); 119 120static inline bool 121inUserMode(CPSR cpsr) 122{
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121 return cpsr.mode == MODE_USER;
| 123 return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
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122} 123 124static inline bool 125inUserMode(ThreadContext *tc) 126{ 127 return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR)); 128} 129 130static inline bool 131inPrivilegedMode(CPSR cpsr) 132{ 133 return !inUserMode(cpsr); 134} 135 136static inline bool 137inPrivilegedMode(ThreadContext *tc) 138{ 139 return !inUserMode(tc); 140} 141
| 124} 125 126static inline bool 127inUserMode(ThreadContext *tc) 128{ 129 return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR)); 130} 131 132static inline bool 133inPrivilegedMode(CPSR cpsr) 134{ 135 return !inUserMode(cpsr); 136} 137 138static inline bool 139inPrivilegedMode(ThreadContext *tc) 140{ 141 return !inUserMode(tc); 142} 143
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142static inline bool 143vfpEnabled(CPACR cpacr, CPSR cpsr)
| 144bool inAArch64(ThreadContext *tc); 145 146static inline OperatingMode 147currOpMode(ThreadContext *tc)
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144{
| 148{
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145 return cpacr.cp10 == 0x3 || 146 (cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr));
| 149 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 150 return (OperatingMode) (uint8_t) cpsr.mode;
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147} 148
| 151} 152
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| 153static inline ExceptionLevel 154currEL(ThreadContext *tc) 155{ 156 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 157 return (ExceptionLevel) (uint8_t) cpsr.el; 158} 159 160bool ELIs64(ThreadContext *tc, ExceptionLevel el); 161 162bool isBigEndian64(ThreadContext *tc); 163 164/** 165 * Removes the tag from tagged addresses if that mode is enabled. 166 * @param addr The address to be purified. 167 * @param tc The thread context. 168 * @param el The controlled exception level. 169 * @return The purified address. 170 */ 171Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el); 172
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149static inline bool
| 173static inline bool
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150vfpEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
| 174inSecureState(SCR scr, CPSR cpsr)
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151{
| 175{
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152 if ((cpacr.cp11 == 0x3) || 153 ((cpacr.cp11 == 0x1) && inPrivilegedMode(cpsr))) 154 return fpexc.en && vfpEnabled(cpacr, cpsr); 155 else 156 return fpexc.en && vfpEnabled(cpacr, cpsr) && 157 (cpacr.cp11 == cpacr.cp10);
| 176 switch ((OperatingMode) (uint8_t) cpsr.mode) { 177 case MODE_MON: 178 case MODE_EL3T: 179 case MODE_EL3H: 180 return true; 181 case MODE_HYP: 182 case MODE_EL2T: 183 case MODE_EL2H: 184 return false; 185 default: 186 return !scr.ns; 187 }
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158} 159
| 188} 189
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| 190bool longDescFormatInUse(ThreadContext *tc); 191 192bool inSecureState(ThreadContext *tc); 193 194uint32_t getMPIDR(ArmSystem *arm_sys, ThreadContext *tc); 195 196static inline uint32_t 197mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn, 198 uint32_t opc1, uint32_t opc2) 199{ 200 return (isRead << 0) | 201 (crm << 1) | 202 (rt << 5) | 203 (crn << 10) | 204 (opc1 << 14) | 205 (opc2 << 17); 206} 207 208static inline void 209mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, 210 uint32_t &crn, uint32_t &opc1, uint32_t &opc2) 211{ 212 isRead = (iss >> 0) & 0x1; 213 crm = (iss >> 1) & 0xF; 214 rt = (IntRegIndex) ((iss >> 5) & 0xF); 215 crn = (iss >> 10) & 0xF; 216 opc1 = (iss >> 14) & 0x7; 217 opc2 = (iss >> 17) & 0x7; 218} 219 220static inline uint32_t 221mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2, 222 uint32_t opc1) 223{ 224 return (isRead << 0) | 225 (crm << 1) | 226 (rt << 5) | 227 (rt2 << 10) | 228 (opc1 << 16); 229} 230 231static inline uint32_t 232msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, 233 uint32_t crm, uint32_t op2, IntRegIndex rt) 234{ 235 return isRead | 236 (crm << 1) | 237 (rt << 5) | 238 (crn << 10) | 239 (op1 << 14) | 240 (op2 << 17) | 241 (op0 << 20); 242} 243 244bool 245mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, 246 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss); 247bool 248mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, 249 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss); 250bool 251mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr, 252 HCR hcr, uint32_t iss); 253 254bool msrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el, 255 CPACR cpacr); 256bool msrMrs64TrapToHyp(const MiscRegIndex miscReg, bool isRead, CPTR cptr, 257 HCR hcr, bool * isVfpNeon); 258bool msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr, 259 ExceptionLevel el, bool * isVfpNeon); 260 261bool 262vfpNeonEnabled(uint32_t &seq, HCPTR hcptr, NSACR nsacr, CPACR cpacr, CPSR cpsr, 263 uint32_t &iss, bool &trap, ThreadContext *tc, 264 FPEXC fpexc = (1<<30), bool isSIMD = false); 265
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160static inline bool
| 266static inline bool
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161neonEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
| 267vfpNeon64Enabled(CPACR cpacr, ExceptionLevel el)
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162{
| 268{
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163 return !cpacr.asedis && vfpEnabled(cpacr, cpsr, fpexc);
| 269 if ((el == EL0 && cpacr.fpen != 0x3) || 270 (el == EL1 && !(cpacr.fpen & 0x1))) 271 return false; 272 return true;
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164} 165
| 273} 274
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| 275bool SPAlignmentCheckEnabled(ThreadContext* tc); 276
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166uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 167 168void skipFunction(ThreadContext *tc); 169 170inline void 171advancePC(PCState &pc, const StaticInstPtr inst) 172{ 173 inst->advancePC(pc); 174} 175 176Addr truncPage(Addr addr); 177Addr roundPage(Addr addr); 178 179inline uint64_t 180getExecutingAsid(ThreadContext *tc) 181{ 182 return tc->readMiscReg(MISCREG_CONTEXTIDR); 183} 184
| 277uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 278 279void skipFunction(ThreadContext *tc); 280 281inline void 282advancePC(PCState &pc, const StaticInstPtr inst) 283{ 284 inst->advancePC(pc); 285} 286 287Addr truncPage(Addr addr); 288Addr roundPage(Addr addr); 289 290inline uint64_t 291getExecutingAsid(ThreadContext *tc) 292{ 293 return tc->readMiscReg(MISCREG_CONTEXTIDR); 294} 295
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| 296// Decodes the register index to access based on the fields used in a MSR 297// or MRS instruction 298bool 299decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx, 300 CPSR cpsr, SCR scr, NSACR nsacr, 301 bool checkSecurity = true); 302 303// This wrapper function is used to turn the register index into a source 304// parameter for the instruction. See Operands.isa 305static inline int 306decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r) 307{ 308 int regIdx; 309 bool isIntReg; 310 bool validReg; 311 312 validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0, false); 313 return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
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185} 186
| 314} 315
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| 316/** 317 * Returns the n. of PA bits corresponding to the specified encoding. 318 */ 319int decodePhysAddrRange64(uint8_t pa_enc); 320 321/** 322 * Returns the encoding corresponding to the specified n. of PA bits. 323 */ 324uint8_t encodePhysAddrRange64(int pa_size); 325 326} 327
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187#endif
| 328#endif
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